Release of the VE2302 Development Kit and VE2302 SOM - Technical Documents

iksevas 1 month ago

Brand new forum covering the release of the VE2302 Development Kit and the Versal AI Edge VE2302 SOM by Avnet / Tria-Technologies. Please ask any questions you have here when you get the chance!

Available documents are at the product page websites:

http://avnet.me/ve2302-dk

http://avnet.me/ve2302-som

Documentation that is currently publicly available is at TECHNICAL DOCUMENTS tab on those web pages. Scroll / navigate around and you should find them.

There is a BDF (board definition file) posted to the Avnet Github: Avnet/bdf: Avnet Board Definition Files

There are also a couple of repositories covering the VE2302 OOB for HW and PETALINUX in the Avnet GITHUB. This design is used for the Getting Started Guide.

More reference designs will begin to be posted to the sites / repos as they become available.

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dyessgg 1 month ago

Pricing and availability?
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dyessgg 1 month ago in reply to dyessgg

I found it after clicking through 3 links. 29 Weeks and $1,850 for the development kit. Not a bad price for a Versal chip.
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iksevas 1 month ago in reply to dyessgg

PNs:

AES-VE2302-DK-G for Development Kit

100-kits (SOM/Carrier Card) scheduled to arrive mid-March over don’t run into issues with PCB procurement.
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jhou 1 month ago

Hi, can you also release schematics? I will need details of pin positions and ref clocks to bring up peripherals, not just board files.
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smsommer 1 month ago

Do you have an Embedded Platform (.xpfm) available for Vitis for the out-of-box reference design?
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jhou 1 month ago in reply to smsommer

Thanks for responding. I installed your board files and created a Vivado project based on DK carrier platform. Vivado is now happy. Jtag sees ve2302 ok. But to go next step such as bringing up MRMAC, I need to know what clocks, pin positions, DDR components, GPIOs, it is importamt to have schematics in hand to assign ios and probe. I do not have your reference build.
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iksevas 1 month ago in reply to jhou

All information you seek is available in User Guide.

Using reference carrier card, MRMAC would probably need to target HSIO expansion interface I believe as other interfaces targeting the GTs map to the HDMI and SFPs.

Unfortunately, schematics are only available when you are working through Avnet related sales/field engineering team.

We will be posting a master constraint file which will have interfaces separated and IO associated from the SOM connectors to the available carrier card peripherals.
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iksevas 1 month ago in reply to smsommer

I have never actually been asked to deliver an XPFM fle to someone. Specifically, we have not attempted to use the Out of Box XSA from Vivado to create a PLATFORM in Vitis. We specifically targeted Petalinux and apps from Linux.
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kboal 1 month ago

Another request for schematics please. We need this information to determine I/O location constraints for our custom design that we are prototyping on this board and more broadly for when we integrate the SOM onto a custom board.
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iksevas 1 month ago in reply to kboal

Please review all of the available user guides (SOM, Carrier Card, as well as CC Design Guide). All pinning information and schematic snippets exist there. As mentioned previously we are working to post a master constraints file that will aid customers in building their own Vivado designs. This is due soon.

otherwise, for schematics you need to get with your local field engineering team for Avnet who can submit an official request for the schematics pdf.
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