Here is a simple correction for the above comment:
After then by using Zynqgeek's bypassing the 12 MIO pins to EMIO and PL part. And using our custom IP for our application.
needs to be changed as
After then by "using Zynqgeek's bypassing the 12 MIO pins to EMIO and PL part. And using our custom IP for our application" we can maybe have ability to use our custom PL IP over the on-board PHY interface.
Here is a simple correction for the above comment:
After then by using Zynqgeek's bypassing the 12 MIO pins to EMIO and PL part. And using our custom IP for our application.
needs to be changed as
After then by "using Zynqgeek's bypassing the 12 MIO pins to EMIO and PL part. And using our custom IP for our application" we can maybe have ability to use our custom PL IP over the on-board PHY interface.
