If you firmiliar with ISE tools and VHDL/Verilog design, that would not be a problem. If you are completely new guy,trying to ask some experienced people is a better choice.
Actually after looking at it that's not quite what I want to do. We have a GigE PHY connected to the MIO pins, but instead of connecting it to the micro's MAC, we want to route the signals to the fabric, and implement a custom MAC there. So is there a way to route the MIO pins to the EMIO pins (bypassing the PS) ?
+1 We are also interested in routing wires from PHY to PL and implement our MAC.
ZynqGeek, you as usual did a great job, but it's not clear how to config MAC if we route signals from it to PL. Because I do not see an config vectors inputs or config interface to Zynq's embedded MAC.
I am trying to build an equivalent to Simulink FPGA-in-the-Loop (FIL) for the Zedboard. Does anyone have a precanned project, such as a simple FIFO, which accomplishes this, i.e., sending data from a host-based Simulink model to and from the FPGA logic, via an Ethernet stack?
Max, Did you ever get a response? I'm trying to do the same thing, to build a simple Ethernet module that can drop packets we dont want to pass to the PS. Thanks, TMB
Unfortunately, this is not possible. To use ZedBoard for this, you'd need to look for an FMC with an Ethernet PHY on it. You cannot connect PL to MIO pins.
What a about a PS application which only configures the Marvell's PHY IC. After then by using Zynqgeek's bypassing the 12 MIO pins to EMIO and PL part. And using our custom IP for our application.
PS: When asking this question i don't have knowledge about the below question: - When our custom IP is doing its job, is there are function of the MDIO and MDC pins for PHY IC?
Sorry for this question. But we have time line and want to get ethernet camera's image information and add some simple additions to the image and show this image on a DMA or HDMI screen. So, we don't have time to learn PS part's coding. If simply configuring the PHY can solve our needs, then we thought that we can use ZB's PHY interface with PL side IP's.
You know "fpgadeveloper.com" like cards offers PL side solutions. If ZB can meet our requirements we won't think about adding extra HWs.
Here is a simple correction for the above comment:
After then by using Zynqgeek's bypassing the 12 MIO pins to EMIO and PL part. And using our custom IP for our application.
needs to be changed as
After then by "using Zynqgeek's bypassing the 12 MIO pins to EMIO and PL part. And using our custom IP for our application" we can maybe have ability to use our custom PL IP over the on-board PHY interface.
