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Zedboard CTT and IOSTANDARD and LOC problems.

Former Member

I'm going thru Zedboard_CTT_v2013_2_120807 tutorial using Vivado2013.4 and I'm stuck at 5.4 - Controlling LED's and Switches in Linux example.

I built a design and ran thru Synthesis and Implementations successfully, but failed to generate bitstream with 2 errors:
1 - [Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 21 out of 151 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value...
2 - [Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 21 out of 151 logical ports have no user assigned specific location constraint (LOC).


Am I missing something?


I googled the topic and looks like I have to add constraints like it mentioned here: http://zedboard.org/content/ise-146-missing-leds8bits-btns5bits-sws8bits


But... First, why it is not mentioned in a tutorial? Second, looks like LED's and Buttons conneted to 3.3V and Switches can be selected by VADJ on Zedboard(on my 3V3 jumper not even populated, so its either 1.8V or 2.5V) and in a post above it suggested to specify 3.3 for all pins. So, I got a little confused and really don't want to damage the board.


Also, in CCT offset address for leds_8bits, btns_5bit and switched_8bit differ from "Basic Vivado IPI Design" example. Why? Which one correct and how/where I can find out the correct offsets without asking here?


Can anybody clarify situation. Thank you in advance.

  • 0

    I was able to implement the hardware for the tutorial using Vivado 2013.4 with no issues.

     

    Since the LEDs, Switches, and buttons are all part of the ZedBoard preset, as long as you did select and enable the ZedBoard preset in step 6, running the Design Automation step will have set the correct constraints for these ports. If you look at the ZedBoard HW Users Guide (on this page http://zedboard.org/documentation/1521) Figure 2 illustrates that the LEDs are on Bank13, which is set to 3.3V and the switches and buttons are on Banks 34 and 35, which are set to 2.5V in the constraints by default. Once you have implemented your design you can select the 'Device Constraints' tab in the Vivado Implemented Design view and select each of the IO Banks to see which signals are assigned to each bank and what IO constraints were generated for each bank/port.

     

    The link you found is for the PlanAhead/ISE tool suite and the .ucf file used by that set of tools, not the .xdc file used by Vivado.

     

    I assume they had you set the address offsets to match whatever the software they plan to use to exercise the LEDs and switchs is expecting.

     

    You may want to take a look at the example ZedBoard Master XDC Constraints file, also on the ZedBoard docs page: http://zedboard.org/documentation/1521

     

    Go back through the tutorial steps carefully and you should be able to build the platform sucessfully with Vivado 2013.4. That said, you may run into other issues in the tutorial since it was developed for Vivado 2013.2 and you may need to make some adjustments for differences in the tool versions.

     

    -Gary

  • 0

    Confirmed.

    I'm positive I did use "Preset" in a step6, but after recreated design one more time I was able to generate "bitstream" without manually settings constrains. Idk what went wrong.

    I guess in a future I will go twice thru each step :)

    Thank you.

  • 0 in reply to Former Member

    i'm not sure but this might help some people,
    i ran into the same sort of problems while i was following different tutorials,
    be careful when you start creating a new project and creating a new h/w specification, when you call for the board template you are using, it may propose different kind of basic IO featured on the board.
    For instance i use the zedboard and the template loads an XML which says that we have 5 BTNS, 8 SWs, 8LEDS on the programmable logic.

    But when you want to start interacting with these, you have to specify a LOC in an UCF file.
    If you called the template, netting inside the ucf file will lead to a conflict.

    I prefer removing any IO and starting with the naked board. Then i create a proper ucf file for every .bitstream made of every single net that i need.

  • 0

    Hello all,

    I am unable to see signal behavior on led , as i am using zedboard so there are some dedicated pins for LED.

    Even before that i wanted to see output signals on zedboard pmod pins but i did not get on pmod pins.

  • 0 in reply to Former Member

    Your post seems to be unrelated to the current thread. If you have a question please start a new forum post and give a little more detail on what you are trying to do and what the issue is.

     

    -Gary