Hi
I tried to add two inputs and save the result into shift reg.
If shift reg is full, then I want "CDMA" between shift reg and DDR3.
So, I added GPIO for external port to connect this port with "adder"
Then, I connected to shift register
Also, in XPS I used CDMA tutorial design (CDMA tutorial UG873 == DDR3 --> DDR3 data transfer).
GP0 -- interconnect -- GPIO ---- ADDER --- shift_reg
HP0 & HP2 --interconnect --CDMA
--------------------------- ------------------------
----------PS---------------- ------------PL-----------
However, I got error about constraint .UCF
which is
/////////////////////////////////////////////////////////////
ERROR:Bitgen:342 - This design contains pins which have locations (LOC) that are
not user-assigned or I/O Standards (IOSTANDARD) that are not user-assigned.
This may cause I/O contention or incompatibility with the board power or
connectivity affecting performance, signal integrity or in extreme cases
cause damage to the device or the components to which it is connected. To
prevent this error, it is highly suggested to specify all pin locations and
I/O standards to avoid potential contention or conflicts and allow proper
bitstream creation. To demote this error to a warning and allow bitstream
creation with unspecified I/O location or standards, you may apply the
following bitgen switch: -g UnconstrainedPins:Allow
//////////////////////////////////////////////////////////////
I don't know how to fix it...(Also, I am not sure my thought is right choice or not)
it seems that somehow I have to make constraint file.
Can someone help me to make .UCF file?
or is there better idea to design for my purpose?
Second, I got fft ip(belfft) from this website. it generates own IP. I am trying to add this IP in PS level (in XPS).
when I try to synthesize and bit generate, it didn't show any errors.
So, I want to add this FFT IP in CDMA design in XPS.
this is original CDMA tutorial example
M_GP0 --- interconnect_gp --- S_CDMA_M ----interconnect_hp -- S_HP0 & S_HP2 ---- DDR3
and this is my expected design.
(FFT --> save into BRAM --> interrupt @ CDMA --> BRAM to DDR3)
which position do I need to consider for FFT IP, BRAM controller, and BRAM?
