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AXI VDMA

Former Member

Hello,

I am having a problem with a simple design on the zedboard. My design consists of a Zynq processor, AXI VDMA, and a AXI TPG. The axi stream clock is set to run at 150Mhz (142.85Mhz actual). The problem is when I synthesize the design it fails timing. The AXI VDMA product guide PG020 shows that the Artix-7 family -1 speed grade can do 150 MHz AXI4-stream.

These are links of images for the timing report.
postimg.org/image/mx3xzenji
postimg.org/image/c206c42p3

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    I tried putting in a clock wizard module and feed it 100MHz in and it produced 148.5MHz using the MCMM setting. I still however have the problem with timing. I am not sure what constraints to put into a constrain file for this design. I have looked over the constraints from the "Zedboard HDMI Display Controller Tutorial for Vivado" as well as the FMC_IMAGEON and t looks very similar, mostly io pin placement and defining the clocks that come off the PS. The reason I started trying to get 148.5MHz from the axi stream was the following. I had it operating at 100MHz and 320x240 frame and VDMA into ddr. The image was fine. Then when i changed the frame size to 1920x1080 every time the vdma would run it would alternate between proper data and garbage data. The vdma is only writing 1 frame. The current constraints that are auto generated by the probject are below.

    On a side note. I have a problem running any of the video examples due to a license problem with vivado. I have downloaded the evaluation license but it never seems to work. When I generate it get errors based on v_spec, v_cfa, etc.



    system_ooc.xdc
    create_clock -name processing_system7_0_FCLK_CLK0 -period 10 [get_pins processing_system7_0/FCLK_CLK0]


    system_axi_vdma_0_0_clocks.xdc


    system_axi_vdma_0_0_ooc.xdc
    create_clock -name s_axi_lite_aclk -period 50 [get_ports s_axi_lite_aclk]
    set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports s_axi_lite_aclk]
    create_clock -name m_axi_s2mm_aclk -period 10 [get_ports m_axi_s2mm_aclk]
    set_property HD.CLK_SRC BUFGCTRL_X0Y2 [get_ports m_axi_s2mm_aclk]
    create_clock -name s_axis_s2mm_aclk -period 20 [get_ports s_axis_s2mm_aclk]
    set_property HD.CLK_SRC BUFGCTRL_X0Y5 [get_ports s_axis_s2mm_aclk]


    system_axi_vdma_0_0.xdc
    set_false_path -to [get_pins -leaf -of_objects [get_cells -hier *cdc_tig* -filter {is_sequential}] -filter {NAME=~*/D}]
    set_false_path -from [get_cells -hier *cdc_from* -filter {is_sequential}] -to [get_cells -hier *cdc_to* -filter {is_sequential}]
      set_false_path -to   [get_pins  -hierarchical  -filter {NAME =~*S2MM*LB_BUILT_IN*/*rstbt*/*PRE}]
      set_false_path -from [get_cells -hierarchical  -filter {NAME =~*S2MM*LB_BUILT_IN*/*rstbt*/*rst_reg_reg && IS_SEQUENTIAL}]
      set_false_path -from [get_cells -hierarchical  -filter {NAME =~*S2MM*LB_BUILT_IN*/*rstbt*/*rst_reg[*]}]


    system_processing_system7_0_0.xdc
    create_clock -name clk_fpga_0 -period "10" [get_pins "PS7_i/FCLKCLK[0]"]
    set_input_jitter clk_fpga_0 0.3
    set_property iostandard "LVCMOS18" [get_ports "MIO[53]"]
    set_property PACKAGE_PIN "C12" [get_ports "MIO[53]"]
    set_property slew "slow" [get_ports "MIO[53]"]
    set_property drive "8" [get_ports "MIO[53]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[53]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[52]"]
    set_property PACKAGE_PIN "D10" [get_ports "MIO[52]"]
    set_property slew "slow" [get_ports "MIO[52]"]
    set_property drive "8" [get_ports "MIO[52]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[52]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[51]"]
    set_property PACKAGE_PIN "C10" [get_ports "MIO[51]"]
    set_property slew "slow" [get_ports "MIO[51]"]
    set_property drive "8" [get_ports "MIO[51]"]
    set_property PIO_DIRECTION "INPUT" [get_ports "MIO[51]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[50]"]
    set_property PACKAGE_PIN "D13" [get_ports "MIO[50]"]
    set_property slew "slow" [get_ports "MIO[50]"]
    set_property drive "8" [get_ports "MIO[50]"]
    set_property PIO_DIRECTION "INPUT" [get_ports "MIO[50]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[49]"]
    set_property PACKAGE_PIN "C14" [get_ports "MIO[49]"]
    set_property slew "slow" [get_ports "MIO[49]"]
    set_property drive "8" [get_ports "MIO[49]"]
    set_property PIO_DIRECTION "INPUT" [get_ports "MIO[49]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[48]"]
    set_property PACKAGE_PIN "D11" [get_ports "MIO[48]"]
    set_property slew "slow" [get_ports "MIO[48]"]
    set_property drive "8" [get_ports "MIO[48]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[48]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[47]"]
    set_property PACKAGE_PIN "B10" [get_ports "MIO[47]"]
    set_property slew "slow" [get_ports "MIO[47]"]
    set_property drive "8" [get_ports "MIO[47]"]
    set_property PIO_DIRECTION "INPUT" [get_ports "MIO[47]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[46]"]
    set_property PACKAGE_PIN "D12" [get_ports "MIO[46]"]
    set_property slew "slow" [get_ports "MIO[46]"]
    set_property drive "8" [get_ports "MIO[46]"]
    set_property PIO_DIRECTION "INPUT" [get_ports "MIO[46]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[45]"]
    set_property PACKAGE_PIN "B9" [get_ports "MIO[45]"]
    set_property slew "fast" [get_ports "MIO[45]"]
    set_property drive "8" [get_ports "MIO[45]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[45]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[44]"]
    set_property PACKAGE_PIN "E13" [get_ports "MIO[44]"]
    set_property slew "fast" [get_ports "MIO[44]"]
    set_property drive "8" [get_ports "MIO[44]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[44]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[43]"]
    set_property PACKAGE_PIN "B11" [get_ports "MIO[43]"]
    set_property slew "fast" [get_ports "MIO[43]"]
    set_property drive "8" [get_ports "MIO[43]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[43]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[42]"]
    set_property PACKAGE_PIN "D8" [get_ports "MIO[42]"]
    set_property slew "fast" [get_ports "MIO[42]"]
    set_property drive "8" [get_ports "MIO[42]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[42]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[41]"]
    set_property PACKAGE_PIN "C8" [get_ports "MIO[41]"]
    set_property slew "fast" [get_ports "MIO[41]"]
    set_property drive "8" [get_ports "MIO[41]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[41]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[40]"]
    set_property PACKAGE_PIN "E14" [get_ports "MIO[40]"]
    set_property slew "fast" [get_ports "MIO[40]"]
    set_property drive "8" [get_ports "MIO[40]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[40]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[39]"]
    set_property PACKAGE_PIN "C13" [get_ports "MIO[39]"]
    set_property slew "fast" [get_ports "MIO[39]"]
    set_property drive "8" [get_ports "MIO[39]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[39]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[38]"]
    set_property PACKAGE_PIN "F13" [get_ports "MIO[38]"]
    set_property slew "fast" [get_ports "MIO[38]"]
    set_property drive "8" [get_ports "MIO[38]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[38]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[37]"]
    set_property PACKAGE_PIN "B14" [get_ports "MIO[37]"]
    set_property slew "fast" [get_ports "MIO[37]"]
    set_property drive "8" [get_ports "MIO[37]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[37]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[36]"]
    set_property PACKAGE_PIN "A9" [get_ports "MIO[36]"]
    set_property slew "fast" [get_ports "MIO[36]"]
    set_property drive "8" [get_ports "MIO[36]"]
    set_property PIO_DIRECTION "INPUT" [get_ports "MIO[36]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[35]"]
    set_property PACKAGE_PIN "F14" [get_ports "MIO[35]"]
    set_property slew "fast" [get_ports "MIO[35]"]
    set_property drive "8" [get_ports "MIO[35]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[35]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[34]"]
    set_property PACKAGE_PIN "B12" [get_ports "MIO[34]"]
    set_property slew "fast" [get_ports "MIO[34]"]
    set_property drive "8" [get_ports "MIO[34]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[34]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[33]"]
    set_property PACKAGE_PIN "G13" [get_ports "MIO[33]"]
    set_property slew "fast" [get_ports "MIO[33]"]
    set_property drive "8" [get_ports "MIO[33]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[33]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[32]"]
    set_property PACKAGE_PIN "C7" [get_ports "MIO[32]"]
    set_property slew "fast" [get_ports "MIO[32]"]
    set_property drive "8" [get_ports "MIO[32]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[32]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[31]"]
    set_property PACKAGE_PIN "F9" [get_ports "MIO[31]"]
    set_property slew "fast" [get_ports "MIO[31]"]
    set_property drive "8" [get_ports "MIO[31]"]
    set_property PIO_DIRECTION "INPUT" [get_ports "MIO[31]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[30]"]
    set_property PACKAGE_PIN "A11" [get_ports "MIO[30]"]
    set_property slew "fast" [get_ports "MIO[30]"]
    set_property drive "8" [get_ports "MIO[30]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[30]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[29]"]
    set_property PACKAGE_PIN "E8" [get_ports "MIO[29]"]
    set_property slew "fast" [get_ports "MIO[29]"]
    set_property drive "8" [get_ports "MIO[29]"]
    set_property PIO_DIRECTION "INPUT" [get_ports "MIO[29]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[28]"]
    set_property PACKAGE_PIN "A12" [get_ports "MIO[28]"]
    set_property slew "fast" [get_ports "MIO[28]"]
    set_property drive "8" [get_ports "MIO[28]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[28]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[27]"]
    set_property PACKAGE_PIN "D7" [get_ports "MIO[27]"]
    set_property slew "fast" [get_ports "MIO[27]"]
    set_property drive "8" [get_ports "MIO[27]"]
    set_property PIO_DIRECTION "INPUT" [get_ports "MIO[27]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[26]"]
    set_property PACKAGE_PIN "A13" [get_ports "MIO[26]"]
    set_property slew "fast" [get_ports "MIO[26]"]
    set_property drive "8" [get_ports "MIO[26]"]
    set_property PIO_DIRECTION "INPUT" [get_ports "MIO[26]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[25]"]
    set_property PACKAGE_PIN "F12" [get_ports "MIO[25]"]
    set_property slew "fast" [get_ports "MIO[25]"]
    set_property drive "8" [get_ports "MIO[25]"]
    set_property PIO_DIRECTION "INPUT" [get_ports "MIO[25]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[24]"]
    set_property PACKAGE_PIN "B7" [get_ports "MIO[24]"]
    set_property slew "fast" [get_ports "MIO[24]"]
    set_property drive "8" [get_ports "MIO[24]"]
    set_property PIO_DIRECTION "INPUT" [get_ports "MIO[24]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[23]"]
    set_property PACKAGE_PIN "E11" [get_ports "MIO[23]"]
    set_property slew "fast" [get_ports "MIO[23]"]
    set_property drive "8" [get_ports "MIO[23]"]
    set_property PIO_DIRECTION "INPUT" [get_ports "MIO[23]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[22]"]
    set_property PACKAGE_PIN "A14" [get_ports "MIO[22]"]
    set_property slew "fast" [get_ports "MIO[22]"]
    set_property drive "8" [get_ports "MIO[22]"]
    set_property PIO_DIRECTION "INPUT" [get_ports "MIO[22]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[21]"]
    set_property PACKAGE_PIN "F11" [get_ports "MIO[21]"]
    set_property slew "fast" [get_ports "MIO[21]"]
    set_property drive "8" [get_ports "MIO[21]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[21]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[20]"]
    set_property PACKAGE_PIN "A8" [get_ports "MIO[20]"]
    set_property slew "fast" [get_ports "MIO[20]"]
    set_property drive "8" [get_ports "MIO[20]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[20]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[19]"]
    set_property PACKAGE_PIN "E10" [get_ports "MIO[19]"]
    set_property slew "fast" [get_ports "MIO[19]"]
    set_property drive "8" [get_ports "MIO[19]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[19]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[18]"]
    set_property PACKAGE_PIN "A7" [get_ports "MIO[18]"]
    set_property slew "fast" [get_ports "MIO[18]"]
    set_property drive "8" [get_ports "MIO[18]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[18]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[17]"]
    set_property PACKAGE_PIN "E9" [get_ports "MIO[17]"]
    set_property slew "fast" [get_ports "MIO[17]"]
    set_property drive "8" [get_ports "MIO[17]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[17]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[16]"]
    set_property PACKAGE_PIN "D6" [get_ports "MIO[16]"]
    set_property slew "fast" [get_ports "MIO[16]"]
    set_property drive "8" [get_ports "MIO[16]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[16]"]
    set_property iostandard "LVCMOS33" [get_ports "MIO[15]"]
    set_property PACKAGE_PIN "E6" [get_ports "MIO[15]"]
    set_property slew "slow" [get_ports "MIO[15]"]
    set_property drive "8" [get_ports "MIO[15]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[15]"]
    set_property iostandard "LVCMOS33" [get_ports "MIO[14]"]
    set_property PACKAGE_PIN "B6" [get_ports "MIO[14]"]
    set_property slew "slow" [get_ports "MIO[14]"]
    set_property drive "8" [get_ports "MIO[14]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[14]"]
    set_property iostandard "LVCMOS33" [get_ports "MIO[13]"]
    set_property PACKAGE_PIN "A6" [get_ports "MIO[13]"]
    set_property slew "slow" [get_ports "MIO[13]"]
    set_property drive "8" [get_ports "MIO[13]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[13]"]
    set_property iostandard "LVCMOS33" [get_ports "MIO[12]"]
    set_property PACKAGE_PIN "C5" [get_ports "MIO[12]"]
    set_property slew "slow" [get_ports "MIO[12]"]
    set_property drive "8" [get_ports "MIO[12]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[12]"]
    set_property iostandard "LVCMOS33" [get_ports "MIO[11]"]
    set_property PACKAGE_PIN "B4" [get_ports "MIO[11]"]
    set_property slew "slow" [get_ports "MIO[11]"]
    set_property drive "8" [get_ports "MIO[11]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[11]"]
    set_property iostandard "LVCMOS33" [get_ports "MIO[10]"]
    set_property PACKAGE_PIN "G7" [get_ports "MIO[10]"]
    set_property slew "slow" [get_ports "MIO[10]"]
    set_property drive "8" [get_ports "MIO[10]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[10]"]
    set_property iostandard "LVCMOS33" [get_ports "MIO[9]"]
    set_property PACKAGE_PIN "C4" [get_ports "MIO[9]"]
    set_property slew "slow" [get_ports "MIO[9]"]
    set_property drive "8" [get_ports "MIO[9]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[9]"]
    set_property iostandard "LVCMOS33" [get_ports "MIO[8]"]
    set_property PACKAGE_PIN "E5" [get_ports "MIO[8]"]
    set_property slew "fast" [get_ports "MIO[8]"]
    set_property drive "8" [get_ports "MIO[8]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[8]"]
    set_property iostandard "LVCMOS33" [get_ports "MIO[7]"]
    set_property PACKAGE_PIN "D5" [get_ports "MIO[7]"]
    set_property slew "slow" [get_ports "MIO[7]"]
    set_property drive "8" [get_ports "MIO[7]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[7]"]
    set_property iostandard "LVCMOS33" [get_ports "MIO[6]"]
    set_property PACKAGE_PIN "A4" [get_ports "MIO[6]"]
    set_property slew "fast" [get_ports "MIO[6]"]
    set_property drive "8" [get_ports "MIO[6]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[6]"]
    set_property iostandard "LVCMOS33" [get_ports "MIO[5]"]
    set_property PACKAGE_PIN "A3" [get_ports "MIO[5]"]
    set_property slew "fast" [get_ports "MIO[5]"]
    set_property drive "8" [get_ports "MIO[5]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[5]"]
    set_property iostandard "LVCMOS33" [get_ports "MIO[4]"]
    set_property PACKAGE_PIN "E4" [get_ports "MIO[4]"]
    set_property slew "fast" [get_ports "MIO[4]"]
    set_property drive "8" [get_ports "MIO[4]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[4]"]
    set_property iostandard "LVCMOS33" [get_ports "MIO[3]"]
    set_property PACKAGE_PIN "F6" [get_ports "MIO[3]"]
    set_property slew "fast" [get_ports "MIO[3]"]
    set_property drive "8" [get_ports "MIO[3]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[3]"]
    set_property iostandard "LVCMOS33" [get_ports "MIO[2]"]
    set_property PACKAGE_PIN "A2" [get_ports "MIO[2]"]
    set_property slew "fast" [get_ports "MIO[2]"]
    set_property drive "8" [get_ports "MIO[2]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[2]"]
    set_property iostandard "LVCMOS33" [get_ports "MIO[1]"]
    set_property PACKAGE_PIN "A1" [get_ports "MIO[1]"]
    set_property slew "fast" [get_ports "MIO[1]"]
    set_property drive "8" [get_ports "MIO[1]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[1]"]
    set_property iostandard "LVCMOS33" [get_ports "MIO[0]"]
    set_property PACKAGE_PIN "G6" [get_ports "MIO[0]"]
    set_property slew "slow" [get_ports "MIO[0]"]
    set_property drive "8" [get_ports "MIO[0]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[0]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_VRP"]
    set_property PACKAGE_PIN "N7" [get_ports "DDR_VRP"]
    set_property slew "FAST" [get_ports "DDR_VRP"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRP"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_VRN"]
    set_property PACKAGE_PIN "M7" [get_ports "DDR_VRN"]
    set_property slew "FAST" [get_ports "DDR_VRN"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRN"]
    set_property iostandard "SSTL15" [get_ports "DDR_WEB"]
    set_property PACKAGE_PIN "R4" [get_ports "DDR_WEB"]
    set_property slew "SLOW" [get_ports "DDR_WEB"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_WEB"]
    set_property iostandard "SSTL15" [get_ports "DDR_RAS_n"]
    set_property PACKAGE_PIN "R5" [get_ports "DDR_RAS_n"]
    set_property slew "SLOW" [get_ports "DDR_RAS_n"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_RAS_n"]
    set_property iostandard "SSTL15" [get_ports "DDR_ODT"]
    set_property PACKAGE_PIN "P5" [get_ports "DDR_ODT"]
    set_property slew "SLOW" [get_ports "DDR_ODT"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_ODT"]
    set_property iostandard "SSTL15" [get_ports "DDR_DRSTB"]
    set_property PACKAGE_PIN "F3" [get_ports "DDR_DRSTB"]
    set_property slew "FAST" [get_ports "DDR_DRSTB"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DRSTB"]
    set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[3]"]
    set_property PACKAGE_PIN "V2" [get_ports "DDR_DQS[3]"]
    set_property slew "FAST" [get_ports "DDR_DQS[3]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[3]"]
    set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[2]"]
    set_property PACKAGE_PIN "N2" [get_ports "DDR_DQS[2]"]
    set_property slew "FAST" [get_ports "DDR_DQS[2]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[2]"]
    set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[1]"]
    set_property PACKAGE_PIN "H2" [get_ports "DDR_DQS[1]"]
    set_property slew "FAST" [get_ports "DDR_DQS[1]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[1]"]
    set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[0]"]
    set_property PACKAGE_PIN "C2" [get_ports "DDR_DQS[0]"]
    set_property slew "FAST" [get_ports "DDR_DQS[0]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[0]"]
    set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[3]"]
    set_property PACKAGE_PIN "W2" [get_ports "DDR_DQS_n[3]"]
    set_property slew "FAST" [get_ports "DDR_DQS_n[3]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[3]"]
    set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[2]"]
    set_property PACKAGE_PIN "P2" [get_ports "DDR_DQS_n[2]"]
    set_property slew "FAST" [get_ports "DDR_DQS_n[2]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[2]"]
    set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[1]"]
    set_property PACKAGE_PIN "J2" [get_ports "DDR_DQS_n[1]"]
    set_property slew "FAST" [get_ports "DDR_DQS_n[1]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[1]"]
    set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[0]"]
    set_property PACKAGE_PIN "D2" [get_ports "DDR_DQS_n[0]"]
    set_property slew "FAST" [get_ports "DDR_DQS_n[0]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[0]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[9]"]
    set_property PACKAGE_PIN "G1" [get_ports "DDR_DQ[9]"]
    set_property slew "FAST" [get_ports "DDR_DQ[9]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[9]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[8]"]
    set_property PACKAGE_PIN "G2" [get_ports "DDR_DQ[8]"]
    set_property slew "FAST" [get_ports "DDR_DQ[8]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[8]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[7]"]
    set_property PACKAGE_PIN "F1" [get_ports "DDR_DQ[7]"]
    set_property slew "FAST" [get_ports "DDR_DQ[7]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[7]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[6]"]
    set_property PACKAGE_PIN "F2" [get_ports "DDR_DQ[6]"]
    set_property slew "FAST" [get_ports "DDR_DQ[6]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[6]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[5]"]
    set_property PACKAGE_PIN "E1" [get_ports "DDR_DQ[5]"]
    set_property slew "FAST" [get_ports "DDR_DQ[5]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[5]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[4]"]
    set_property PACKAGE_PIN "E3" [get_ports "DDR_DQ[4]"]
    set_property slew "FAST" [get_ports "DDR_DQ[4]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[4]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[3]"]
    set_property PACKAGE_PIN "D3" [get_ports "DDR_DQ[3]"]
    set_property slew "FAST" [get_ports "DDR_DQ[3]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[3]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[31]"]
    set_property PACKAGE_PIN "Y1" [get_ports "DDR_DQ[31]"]
    set_property slew "FAST" [get_ports "DDR_DQ[31]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[31]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[30]"]
    set_property PACKAGE_PIN "W3" [get_ports "DDR_DQ[30]"]
    set_property slew "FAST" [get_ports "DDR_DQ[30]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[30]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[2]"]
    set_property PACKAGE_PIN "B2" [get_ports "DDR_DQ[2]"]
    set_property slew "FAST" [get_ports "DDR_DQ[2]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[2]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[29]"]
    set_property PACKAGE_PIN "Y3" [get_ports "DDR_DQ[29]"]
    set_property slew "FAST" [get_ports "DDR_DQ[29]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[29]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[28]"]
    set_property PACKAGE_PIN "W1" [get_ports "DDR_DQ[28]"]
    set_property slew "FAST" [get_ports "DDR_DQ[28]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[28]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[27]"]
    set_property PACKAGE_PIN "U2" [get_ports "DDR_DQ[27]"]
    set_property slew "FAST" [get_ports "DDR_DQ[27]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[27]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[26]"]
    set_property PACKAGE_PIN "AA1" [get_ports "DDR_DQ[26]"]
    set_property slew "FAST" [get_ports "DDR_DQ[26]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[26]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[25]"]
    set_property PACKAGE_PIN "U1" [get_ports "DDR_DQ[25]"]
    set_property slew "FAST" [get_ports "DDR_DQ[25]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[25]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[24]"]
    set_property PACKAGE_PIN "AA3" [get_ports "DDR_DQ[24]"]
    set_property slew "FAST" [get_ports "DDR_DQ[24]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[24]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[23]"]
    set_property PACKAGE_PIN "R1" [get_ports "DDR_DQ[23]"]
    set_property slew "FAST" [get_ports "DDR_DQ[23]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[23]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[22]"]
    set_property PACKAGE_PIN "M2" [get_ports "DDR_DQ[22]"]
    set_property slew "FAST" [get_ports "DDR_DQ[22]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[22]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[21]"]
    set_property PACKAGE_PIN "T2" [get_ports "DDR_DQ[21]"]
    set_property slew "FAST" [get_ports "DDR_DQ[21]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[21]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[20]"]
    set_property PACKAGE_PIN "R3" [get_ports "DDR_DQ[20]"]
    set_property slew "FAST" [get_ports "DDR_DQ[20]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[20]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[1]"]
    set_property PACKAGE_PIN "C3" [get_ports "DDR_DQ[1]"]
    set_property slew "FAST" [get_ports "DDR_DQ[1]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[1]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[19]"]
    set_property PACKAGE_PIN "T1" [get_ports "DDR_DQ[19]"]
    set_property slew "FAST" [get_ports "DDR_DQ[19]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[19]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[18]"]
    set_property PACKAGE_PIN "N3" [get_ports "DDR_DQ[18]"]
    set_property slew "FAST" [get_ports "DDR_DQ[18]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[18]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[17]"]
    set_property PACKAGE_PIN "T3" [get_ports "DDR_DQ[17]"]
    set_property slew "FAST" [get_ports "DDR_DQ[17]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[17]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[16]"]
    set_property PACKAGE_PIN "M1" [get_ports "DDR_DQ[16]"]
    set_property slew "FAST" [get_ports "DDR_DQ[16]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[16]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[15]"]
    set_property PACKAGE_PIN "K3" [get_ports "DDR_DQ[15]"]
    set_property slew "FAST" [get_ports "DDR_DQ[15]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[15]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[14]"]
    set_property PACKAGE_PIN "J1" [get_ports "DDR_DQ[14]"]
    set_property slew "FAST" [get_ports "DDR_DQ[14]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[14]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[13]"]
    set_property PACKAGE_PIN "K1" [get_ports "DDR_DQ[13]"]
    set_property slew "FAST" [get_ports "DDR_DQ[13]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[13]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[12]"]
    set_property PACKAGE_PIN "L3" [get_ports "DDR_DQ[12]"]
    set_property slew "FAST" [get_ports "DDR_DQ[12]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[12]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[11]"]
    set_property PACKAGE_PIN "L2" [get_ports "DDR_DQ[11]"]
    set_property slew "FAST" [get_ports "DDR_DQ[11]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[11]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[10]"]
    set_property PACKAGE_PIN "L1" [get_ports "DDR_DQ[10]"]
    set_property slew "FAST" [get_ports "DDR_DQ[10]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[10]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[0]"]
    set_property PACKAGE_PIN "D1" [get_ports "DDR_DQ[0]"]
    set_property slew "FAST" [get_ports "DDR_DQ[0]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[0]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[3]"]
    set_property PACKAGE_PIN "AA2" [get_ports "DDR_DM[3]"]
    set_property slew "FAST" [get_ports "DDR_DM[3]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[3]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[2]"]
    set_property PACKAGE_PIN "P1" [get_ports "DDR_DM[2]"]
    set_property slew "FAST" [get_ports "DDR_DM[2]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[2]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[1]"]
    set_property PACKAGE_PIN "H3" [get_ports "DDR_DM[1]"]
    set_property slew "FAST" [get_ports "DDR_DM[1]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[1]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[0]"]
    set_property PACKAGE_PIN "B1" [get_ports "DDR_DM[0]"]
    set_property slew "FAST" [get_ports "DDR_DM[0]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[0]"]
    set_property iostandard "SSTL15" [get_ports "DDR_CS_n"]
    set_property PACKAGE_PIN "P6" [get_ports "DDR_CS_n"]
    set_property slew "SLOW" [get_ports "DDR_CS_n"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CS_n"]
    set_property iostandard "SSTL15" [get_ports "DDR_CKE"]
    set_property PACKAGE_PIN "V3" [get_ports "DDR_CKE"]
    set_property slew "SLOW" [get_ports "DDR_CKE"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CKE"]
    set_property iostandard "DIFF_SSTL15" [get_ports "DDR_Clk"]
    set_property PACKAGE_PIN "N4" [get_ports "DDR_Clk"]
    set_property slew "FAST" [get_ports "DDR_Clk"]
    set_property PIO_DIRECTION "INPUT" [get_ports "DDR_Clk"]
    set_property iostandard "DIFF_SSTL15" [get_ports "DDR_Clk_n"]
    set_property PACKAGE_PIN "N5" [get_ports "DDR_Clk_n"]
    set_property slew "FAST" [get_ports "DDR_Clk_n"]
    set_property PIO_DIRECTION "INPUT" [get_ports "DDR_Clk_n"]
    set_property iostandard "SSTL15" [get_ports "DDR_CAS_n"]
    set_property PACKAGE_PIN "P3" [get_ports "DDR_CAS_n"]
    set_property slew "SLOW" [get_ports "DDR_CAS_n"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CAS_n"]
    set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[2]"]
    set_property PACKAGE_PIN "M6" [get_ports "DDR_BankAddr[2]"]
    set_property slew "SLOW" [get_ports "DDR_BankAddr[2]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[2]"]
    set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[1]"]
    set_property PACKAGE_PIN "L6" [get_ports "DDR_BankAddr[1]"]
    set_property slew "SLOW" [get_ports "DDR_BankAddr[1]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[1]"]
    set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[0]"]
    set_property PACKAGE_PIN "L7" [get_ports "DDR_BankAddr[0]"]
    set_property slew "SLOW" [get_ports "DDR_BankAddr[0]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[0]"]
    set_property iostandard "SSTL15" [get_ports "DDR_Addr[9]"]
    set_property PACKAGE_PIN "H5" [get_ports "DDR_Addr[9]"]
    set_property slew "SLOW" [get_ports "DDR_Addr[9]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[9]"]
    set_property iostandard "SSTL15" [get_ports "DDR_Addr[8]"]
    set_property PACKAGE_PIN "J5" [get_ports "DDR_Addr[8]"]
    set_property slew "SLOW" [get_ports "DDR_Addr[8]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[8]"]
    set_property iostandard "SSTL15" [get_ports "DDR_Addr[7]"]
    set_property PACKAGE_PIN "J6" [get_ports "DDR_Addr[7]"]
    set_property slew "SLOW" [get_ports "DDR_Addr[7]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[7]"]
    set_property iostandard "SSTL15" [get_ports "DDR_Addr[6]"]
    set_property PACKAGE_PIN "J7" [get_ports "DDR_Addr[6]"]
    set_property slew "SLOW" [get_ports "DDR_Addr[6]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[6]"]
    set_property iostandard "SSTL15" [get_ports "DDR_Addr[5]"]
    set_property PACKAGE_PIN "K5" [get_ports "DDR_Addr[5]"]
    set_property slew "SLOW" [get_ports "DDR_Addr[5]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[5]"]
    set_property iostandard "SSTL15" [get_ports "DDR_Addr[4]"]
    set_property PACKAGE_PIN "K6" [get_ports "DDR_Addr[4]"]
    set_property slew "SLOW" [get_ports "DDR_Addr[4]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[4]"]
    set_property iostandard "SSTL15" [get_ports "DDR_Addr[3]"]
    set_property PACKAGE_PIN "L4" [get_ports "DDR_Addr[3]"]
    set_property slew "SLOW" [get_ports "DDR_Addr[3]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[3]"]
    set_property iostandard "SSTL15" [get_ports "DDR_Addr[2]"]
    set_property PACKAGE_PIN "K4" [get_ports "DDR_Addr[2]"]
    set_property slew "SLOW" [get_ports "DDR_Addr[2]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[2]"]
    set_property iostandard "SSTL15" [get_ports "DDR_Addr[1]"]
    set_property PACKAGE_PIN "M5" [get_ports "DDR_Addr[1]"]
    set_property slew "SLOW" [get_ports "DDR_Addr[1]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[1]"]
    set_property iostandard "SSTL15" [get_ports "DDR_Addr[14]"]
    set_property PACKAGE_PIN "G4" [get_ports "DDR_Addr[14]"]
    set_property slew "SLOW" [get_ports "DDR_Addr[14]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[14]"]
    set_property iostandard "SSTL15" [get_ports "DDR_Addr[13]"]
    set_property PACKAGE_PIN "F4" [get_ports "DDR_Addr[13]"]
    set_property slew "SLOW" [get_ports "DDR_Addr[13]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[13]"]
    set_property iostandard "SSTL15" [get_ports "DDR_Addr[12]"]
    set_property PACKAGE_PIN "H4" [get_ports "DDR_Addr[12]"]
    set_property slew "SLOW" [get_ports "DDR_Addr[12]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[12]"]
    set_property iostandard "SSTL15" [get_ports "DDR_Addr[11]"]
    set_property PACKAGE_PIN "G5" [get_ports "DDR_Addr[11]"]
    set_property slew "SLOW" [get_ports "DDR_Addr[11]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[11]"]
    set_property iostandard "SSTL15" [get_ports "DDR_Addr[10]"]
    set_property PACKAGE_PIN "J3" [get_ports "DDR_Addr[10]"]
    set_property slew "SLOW" [get_ports "DDR_Addr[10]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[10]"]
    set_property iostandard "SSTL15" [get_ports "DDR_Addr[0]"]
    set_property PACKAGE_PIN "M4" [get_ports "DDR_Addr[0]"]
    set_property slew "SLOW" [get_ports "DDR_Addr[0]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[0]"]
    set_property iostandard "LVCMOS33" [get_ports "PS_PORB"]
    set_property PACKAGE_PIN "B5" [get_ports "PS_PORB"]
    set_property slew "slow" [get_ports "PS_PORB"]
    set_property drive "8" [get_ports "PS_PORB"]
    set_property iostandard "LVCMOS33" [get_ports "PS_SRSTB"]
    set_property PACKAGE_PIN "C9" [get_ports "PS_SRSTB"]
    set_property slew "slow" [get_ports "PS_SRSTB"]
    set_property drive "8" [get_ports "PS_SRSTB"]
    set_property iostandard "LVCMOS33" [get_ports "PS_CLK"]
    set_property PACKAGE_PIN "F7" [get_ports "PS_CLK"]
    set_property slew "slow" [get_ports "PS_CLK"]
    set_property drive "8" [get_ports "PS_CLK"]


    system_rst_clk_wiz_0_100M_0_board.xdc


    system_rst_clk_wiz_0_100M_0.xdc
    set_false_path -through [get_ports ext_reset_in]


    system_rst_clk_wiz_0_100M_0_ooc.xdc
    create_clock -name slowest_sync_clk -period 10 [get_ports slowest_sync_clk]


    system_rst_processing_system7_0_100M_1.xdc
    set_false_path -through [get_ports ext_reset_in]


    system_rst_processing_system7_0_100M_1_board.xdc


    system_rst_processing_system7_0_100M_1_ooc.xdc
    create_clock -name slowest_sync_clk -period 10 [get_ports slowest_sync_clk]


    system_auto_us_0_ooc.xdc
    create_clock -period 100.0 -name aclk [get_ports *_axi_aclk]


    system_auto_us_0_clocks.xdc


    system_clk_wiz_0_1.xdc
    create_clock -period 10.0 [get_ports clk_in1]
    set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.1


    system_clk_wiz_0_1_ooc.xdc


    system_clk_wiz_0_1_board.xdc


    system_xbar_0_ooc.xdc
    create_clock -period 100.0 -name aclk [get_ports aclk]


    system_auto_pc_1_ooc.xdc
    create_clock -period 100.0 -name aclk [get_ports aclk]


    system_auto_pc_0_ooc.xdc
    create_clock -period 100.0 -name aclk [get_ports aclk]


    system_v_tpg_0_1_ooc.xdc
    create_clock -name aclk -period 6.734 [get_ports aclk]
    create_clock -name s_axi_aclk -period 10 [get_ports s_axi_aclk]


    system_v_tpg_0_1_clocks.xdc
      set video_clk   [get_clocks -of [get_ports aclk]]
      set axilite_clk [get_clocks -of [get_ports s_axi_aclk]]
      set_max_delay -from $video_clk -to [get_cells -hierarchical -filter {NAME =~ *video_cntrl*/*SYNC2PROCCLK_I*/data_sync_reg[0]*}] -datapath_only [get_property -min PERIOD $video_clk]
      set_max_delay -from $axilite_clk -to [get_cells -hierarchical -filter {NAME =~ *video_cntrl*/*SYNC2VIDCLK_I*/data_sync_reg[0]*}] -datapath_only [get_property -min PERIOD $axilite_clk]

Reply
  • 0

    I tried putting in a clock wizard module and feed it 100MHz in and it produced 148.5MHz using the MCMM setting. I still however have the problem with timing. I am not sure what constraints to put into a constrain file for this design. I have looked over the constraints from the "Zedboard HDMI Display Controller Tutorial for Vivado" as well as the FMC_IMAGEON and t looks very similar, mostly io pin placement and defining the clocks that come off the PS. The reason I started trying to get 148.5MHz from the axi stream was the following. I had it operating at 100MHz and 320x240 frame and VDMA into ddr. The image was fine. Then when i changed the frame size to 1920x1080 every time the vdma would run it would alternate between proper data and garbage data. The vdma is only writing 1 frame. The current constraints that are auto generated by the probject are below.

    On a side note. I have a problem running any of the video examples due to a license problem with vivado. I have downloaded the evaluation license but it never seems to work. When I generate it get errors based on v_spec, v_cfa, etc.



    system_ooc.xdc
    create_clock -name processing_system7_0_FCLK_CLK0 -period 10 [get_pins processing_system7_0/FCLK_CLK0]


    system_axi_vdma_0_0_clocks.xdc


    system_axi_vdma_0_0_ooc.xdc
    create_clock -name s_axi_lite_aclk -period 50 [get_ports s_axi_lite_aclk]
    set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports s_axi_lite_aclk]
    create_clock -name m_axi_s2mm_aclk -period 10 [get_ports m_axi_s2mm_aclk]
    set_property HD.CLK_SRC BUFGCTRL_X0Y2 [get_ports m_axi_s2mm_aclk]
    create_clock -name s_axis_s2mm_aclk -period 20 [get_ports s_axis_s2mm_aclk]
    set_property HD.CLK_SRC BUFGCTRL_X0Y5 [get_ports s_axis_s2mm_aclk]


    system_axi_vdma_0_0.xdc
    set_false_path -to [get_pins -leaf -of_objects [get_cells -hier *cdc_tig* -filter {is_sequential}] -filter {NAME=~*/D}]
    set_false_path -from [get_cells -hier *cdc_from* -filter {is_sequential}] -to [get_cells -hier *cdc_to* -filter {is_sequential}]
      set_false_path -to   [get_pins  -hierarchical  -filter {NAME =~*S2MM*LB_BUILT_IN*/*rstbt*/*PRE}]
      set_false_path -from [get_cells -hierarchical  -filter {NAME =~*S2MM*LB_BUILT_IN*/*rstbt*/*rst_reg_reg && IS_SEQUENTIAL}]
      set_false_path -from [get_cells -hierarchical  -filter {NAME =~*S2MM*LB_BUILT_IN*/*rstbt*/*rst_reg[*]}]


    system_processing_system7_0_0.xdc
    create_clock -name clk_fpga_0 -period "10" [get_pins "PS7_i/FCLKCLK[0]"]
    set_input_jitter clk_fpga_0 0.3
    set_property iostandard "LVCMOS18" [get_ports "MIO[53]"]
    set_property PACKAGE_PIN "C12" [get_ports "MIO[53]"]
    set_property slew "slow" [get_ports "MIO[53]"]
    set_property drive "8" [get_ports "MIO[53]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[53]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[52]"]
    set_property PACKAGE_PIN "D10" [get_ports "MIO[52]"]
    set_property slew "slow" [get_ports "MIO[52]"]
    set_property drive "8" [get_ports "MIO[52]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[52]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[51]"]
    set_property PACKAGE_PIN "C10" [get_ports "MIO[51]"]
    set_property slew "slow" [get_ports "MIO[51]"]
    set_property drive "8" [get_ports "MIO[51]"]
    set_property PIO_DIRECTION "INPUT" [get_ports "MIO[51]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[50]"]
    set_property PACKAGE_PIN "D13" [get_ports "MIO[50]"]
    set_property slew "slow" [get_ports "MIO[50]"]
    set_property drive "8" [get_ports "MIO[50]"]
    set_property PIO_DIRECTION "INPUT" [get_ports "MIO[50]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[49]"]
    set_property PACKAGE_PIN "C14" [get_ports "MIO[49]"]
    set_property slew "slow" [get_ports "MIO[49]"]
    set_property drive "8" [get_ports "MIO[49]"]
    set_property PIO_DIRECTION "INPUT" [get_ports "MIO[49]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[48]"]
    set_property PACKAGE_PIN "D11" [get_ports "MIO[48]"]
    set_property slew "slow" [get_ports "MIO[48]"]
    set_property drive "8" [get_ports "MIO[48]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[48]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[47]"]
    set_property PACKAGE_PIN "B10" [get_ports "MIO[47]"]
    set_property slew "slow" [get_ports "MIO[47]"]
    set_property drive "8" [get_ports "MIO[47]"]
    set_property PIO_DIRECTION "INPUT" [get_ports "MIO[47]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[46]"]
    set_property PACKAGE_PIN "D12" [get_ports "MIO[46]"]
    set_property slew "slow" [get_ports "MIO[46]"]
    set_property drive "8" [get_ports "MIO[46]"]
    set_property PIO_DIRECTION "INPUT" [get_ports "MIO[46]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[45]"]
    set_property PACKAGE_PIN "B9" [get_ports "MIO[45]"]
    set_property slew "fast" [get_ports "MIO[45]"]
    set_property drive "8" [get_ports "MIO[45]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[45]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[44]"]
    set_property PACKAGE_PIN "E13" [get_ports "MIO[44]"]
    set_property slew "fast" [get_ports "MIO[44]"]
    set_property drive "8" [get_ports "MIO[44]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[44]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[43]"]
    set_property PACKAGE_PIN "B11" [get_ports "MIO[43]"]
    set_property slew "fast" [get_ports "MIO[43]"]
    set_property drive "8" [get_ports "MIO[43]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[43]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[42]"]
    set_property PACKAGE_PIN "D8" [get_ports "MIO[42]"]
    set_property slew "fast" [get_ports "MIO[42]"]
    set_property drive "8" [get_ports "MIO[42]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[42]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[41]"]
    set_property PACKAGE_PIN "C8" [get_ports "MIO[41]"]
    set_property slew "fast" [get_ports "MIO[41]"]
    set_property drive "8" [get_ports "MIO[41]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[41]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[40]"]
    set_property PACKAGE_PIN "E14" [get_ports "MIO[40]"]
    set_property slew "fast" [get_ports "MIO[40]"]
    set_property drive "8" [get_ports "MIO[40]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[40]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[39]"]
    set_property PACKAGE_PIN "C13" [get_ports "MIO[39]"]
    set_property slew "fast" [get_ports "MIO[39]"]
    set_property drive "8" [get_ports "MIO[39]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[39]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[38]"]
    set_property PACKAGE_PIN "F13" [get_ports "MIO[38]"]
    set_property slew "fast" [get_ports "MIO[38]"]
    set_property drive "8" [get_ports "MIO[38]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[38]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[37]"]
    set_property PACKAGE_PIN "B14" [get_ports "MIO[37]"]
    set_property slew "fast" [get_ports "MIO[37]"]
    set_property drive "8" [get_ports "MIO[37]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[37]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[36]"]
    set_property PACKAGE_PIN "A9" [get_ports "MIO[36]"]
    set_property slew "fast" [get_ports "MIO[36]"]
    set_property drive "8" [get_ports "MIO[36]"]
    set_property PIO_DIRECTION "INPUT" [get_ports "MIO[36]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[35]"]
    set_property PACKAGE_PIN "F14" [get_ports "MIO[35]"]
    set_property slew "fast" [get_ports "MIO[35]"]
    set_property drive "8" [get_ports "MIO[35]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[35]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[34]"]
    set_property PACKAGE_PIN "B12" [get_ports "MIO[34]"]
    set_property slew "fast" [get_ports "MIO[34]"]
    set_property drive "8" [get_ports "MIO[34]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[34]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[33]"]
    set_property PACKAGE_PIN "G13" [get_ports "MIO[33]"]
    set_property slew "fast" [get_ports "MIO[33]"]
    set_property drive "8" [get_ports "MIO[33]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[33]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[32]"]
    set_property PACKAGE_PIN "C7" [get_ports "MIO[32]"]
    set_property slew "fast" [get_ports "MIO[32]"]
    set_property drive "8" [get_ports "MIO[32]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[32]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[31]"]
    set_property PACKAGE_PIN "F9" [get_ports "MIO[31]"]
    set_property slew "fast" [get_ports "MIO[31]"]
    set_property drive "8" [get_ports "MIO[31]"]
    set_property PIO_DIRECTION "INPUT" [get_ports "MIO[31]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[30]"]
    set_property PACKAGE_PIN "A11" [get_ports "MIO[30]"]
    set_property slew "fast" [get_ports "MIO[30]"]
    set_property drive "8" [get_ports "MIO[30]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[30]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[29]"]
    set_property PACKAGE_PIN "E8" [get_ports "MIO[29]"]
    set_property slew "fast" [get_ports "MIO[29]"]
    set_property drive "8" [get_ports "MIO[29]"]
    set_property PIO_DIRECTION "INPUT" [get_ports "MIO[29]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[28]"]
    set_property PACKAGE_PIN "A12" [get_ports "MIO[28]"]
    set_property slew "fast" [get_ports "MIO[28]"]
    set_property drive "8" [get_ports "MIO[28]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[28]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[27]"]
    set_property PACKAGE_PIN "D7" [get_ports "MIO[27]"]
    set_property slew "fast" [get_ports "MIO[27]"]
    set_property drive "8" [get_ports "MIO[27]"]
    set_property PIO_DIRECTION "INPUT" [get_ports "MIO[27]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[26]"]
    set_property PACKAGE_PIN "A13" [get_ports "MIO[26]"]
    set_property slew "fast" [get_ports "MIO[26]"]
    set_property drive "8" [get_ports "MIO[26]"]
    set_property PIO_DIRECTION "INPUT" [get_ports "MIO[26]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[25]"]
    set_property PACKAGE_PIN "F12" [get_ports "MIO[25]"]
    set_property slew "fast" [get_ports "MIO[25]"]
    set_property drive "8" [get_ports "MIO[25]"]
    set_property PIO_DIRECTION "INPUT" [get_ports "MIO[25]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[24]"]
    set_property PACKAGE_PIN "B7" [get_ports "MIO[24]"]
    set_property slew "fast" [get_ports "MIO[24]"]
    set_property drive "8" [get_ports "MIO[24]"]
    set_property PIO_DIRECTION "INPUT" [get_ports "MIO[24]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[23]"]
    set_property PACKAGE_PIN "E11" [get_ports "MIO[23]"]
    set_property slew "fast" [get_ports "MIO[23]"]
    set_property drive "8" [get_ports "MIO[23]"]
    set_property PIO_DIRECTION "INPUT" [get_ports "MIO[23]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[22]"]
    set_property PACKAGE_PIN "A14" [get_ports "MIO[22]"]
    set_property slew "fast" [get_ports "MIO[22]"]
    set_property drive "8" [get_ports "MIO[22]"]
    set_property PIO_DIRECTION "INPUT" [get_ports "MIO[22]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[21]"]
    set_property PACKAGE_PIN "F11" [get_ports "MIO[21]"]
    set_property slew "fast" [get_ports "MIO[21]"]
    set_property drive "8" [get_ports "MIO[21]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[21]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[20]"]
    set_property PACKAGE_PIN "A8" [get_ports "MIO[20]"]
    set_property slew "fast" [get_ports "MIO[20]"]
    set_property drive "8" [get_ports "MIO[20]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[20]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[19]"]
    set_property PACKAGE_PIN "E10" [get_ports "MIO[19]"]
    set_property slew "fast" [get_ports "MIO[19]"]
    set_property drive "8" [get_ports "MIO[19]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[19]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[18]"]
    set_property PACKAGE_PIN "A7" [get_ports "MIO[18]"]
    set_property slew "fast" [get_ports "MIO[18]"]
    set_property drive "8" [get_ports "MIO[18]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[18]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[17]"]
    set_property PACKAGE_PIN "E9" [get_ports "MIO[17]"]
    set_property slew "fast" [get_ports "MIO[17]"]
    set_property drive "8" [get_ports "MIO[17]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[17]"]
    set_property iostandard "LVCMOS18" [get_ports "MIO[16]"]
    set_property PACKAGE_PIN "D6" [get_ports "MIO[16]"]
    set_property slew "fast" [get_ports "MIO[16]"]
    set_property drive "8" [get_ports "MIO[16]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[16]"]
    set_property iostandard "LVCMOS33" [get_ports "MIO[15]"]
    set_property PACKAGE_PIN "E6" [get_ports "MIO[15]"]
    set_property slew "slow" [get_ports "MIO[15]"]
    set_property drive "8" [get_ports "MIO[15]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[15]"]
    set_property iostandard "LVCMOS33" [get_ports "MIO[14]"]
    set_property PACKAGE_PIN "B6" [get_ports "MIO[14]"]
    set_property slew "slow" [get_ports "MIO[14]"]
    set_property drive "8" [get_ports "MIO[14]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[14]"]
    set_property iostandard "LVCMOS33" [get_ports "MIO[13]"]
    set_property PACKAGE_PIN "A6" [get_ports "MIO[13]"]
    set_property slew "slow" [get_ports "MIO[13]"]
    set_property drive "8" [get_ports "MIO[13]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[13]"]
    set_property iostandard "LVCMOS33" [get_ports "MIO[12]"]
    set_property PACKAGE_PIN "C5" [get_ports "MIO[12]"]
    set_property slew "slow" [get_ports "MIO[12]"]
    set_property drive "8" [get_ports "MIO[12]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[12]"]
    set_property iostandard "LVCMOS33" [get_ports "MIO[11]"]
    set_property PACKAGE_PIN "B4" [get_ports "MIO[11]"]
    set_property slew "slow" [get_ports "MIO[11]"]
    set_property drive "8" [get_ports "MIO[11]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[11]"]
    set_property iostandard "LVCMOS33" [get_ports "MIO[10]"]
    set_property PACKAGE_PIN "G7" [get_ports "MIO[10]"]
    set_property slew "slow" [get_ports "MIO[10]"]
    set_property drive "8" [get_ports "MIO[10]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[10]"]
    set_property iostandard "LVCMOS33" [get_ports "MIO[9]"]
    set_property PACKAGE_PIN "C4" [get_ports "MIO[9]"]
    set_property slew "slow" [get_ports "MIO[9]"]
    set_property drive "8" [get_ports "MIO[9]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[9]"]
    set_property iostandard "LVCMOS33" [get_ports "MIO[8]"]
    set_property PACKAGE_PIN "E5" [get_ports "MIO[8]"]
    set_property slew "fast" [get_ports "MIO[8]"]
    set_property drive "8" [get_ports "MIO[8]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[8]"]
    set_property iostandard "LVCMOS33" [get_ports "MIO[7]"]
    set_property PACKAGE_PIN "D5" [get_ports "MIO[7]"]
    set_property slew "slow" [get_ports "MIO[7]"]
    set_property drive "8" [get_ports "MIO[7]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[7]"]
    set_property iostandard "LVCMOS33" [get_ports "MIO[6]"]
    set_property PACKAGE_PIN "A4" [get_ports "MIO[6]"]
    set_property slew "fast" [get_ports "MIO[6]"]
    set_property drive "8" [get_ports "MIO[6]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[6]"]
    set_property iostandard "LVCMOS33" [get_ports "MIO[5]"]
    set_property PACKAGE_PIN "A3" [get_ports "MIO[5]"]
    set_property slew "fast" [get_ports "MIO[5]"]
    set_property drive "8" [get_ports "MIO[5]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[5]"]
    set_property iostandard "LVCMOS33" [get_ports "MIO[4]"]
    set_property PACKAGE_PIN "E4" [get_ports "MIO[4]"]
    set_property slew "fast" [get_ports "MIO[4]"]
    set_property drive "8" [get_ports "MIO[4]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[4]"]
    set_property iostandard "LVCMOS33" [get_ports "MIO[3]"]
    set_property PACKAGE_PIN "F6" [get_ports "MIO[3]"]
    set_property slew "fast" [get_ports "MIO[3]"]
    set_property drive "8" [get_ports "MIO[3]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[3]"]
    set_property iostandard "LVCMOS33" [get_ports "MIO[2]"]
    set_property PACKAGE_PIN "A2" [get_ports "MIO[2]"]
    set_property slew "fast" [get_ports "MIO[2]"]
    set_property drive "8" [get_ports "MIO[2]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[2]"]
    set_property iostandard "LVCMOS33" [get_ports "MIO[1]"]
    set_property PACKAGE_PIN "A1" [get_ports "MIO[1]"]
    set_property slew "fast" [get_ports "MIO[1]"]
    set_property drive "8" [get_ports "MIO[1]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[1]"]
    set_property iostandard "LVCMOS33" [get_ports "MIO[0]"]
    set_property PACKAGE_PIN "G6" [get_ports "MIO[0]"]
    set_property slew "slow" [get_ports "MIO[0]"]
    set_property drive "8" [get_ports "MIO[0]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[0]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_VRP"]
    set_property PACKAGE_PIN "N7" [get_ports "DDR_VRP"]
    set_property slew "FAST" [get_ports "DDR_VRP"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRP"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_VRN"]
    set_property PACKAGE_PIN "M7" [get_ports "DDR_VRN"]
    set_property slew "FAST" [get_ports "DDR_VRN"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRN"]
    set_property iostandard "SSTL15" [get_ports "DDR_WEB"]
    set_property PACKAGE_PIN "R4" [get_ports "DDR_WEB"]
    set_property slew "SLOW" [get_ports "DDR_WEB"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_WEB"]
    set_property iostandard "SSTL15" [get_ports "DDR_RAS_n"]
    set_property PACKAGE_PIN "R5" [get_ports "DDR_RAS_n"]
    set_property slew "SLOW" [get_ports "DDR_RAS_n"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_RAS_n"]
    set_property iostandard "SSTL15" [get_ports "DDR_ODT"]
    set_property PACKAGE_PIN "P5" [get_ports "DDR_ODT"]
    set_property slew "SLOW" [get_ports "DDR_ODT"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_ODT"]
    set_property iostandard "SSTL15" [get_ports "DDR_DRSTB"]
    set_property PACKAGE_PIN "F3" [get_ports "DDR_DRSTB"]
    set_property slew "FAST" [get_ports "DDR_DRSTB"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DRSTB"]
    set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[3]"]
    set_property PACKAGE_PIN "V2" [get_ports "DDR_DQS[3]"]
    set_property slew "FAST" [get_ports "DDR_DQS[3]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[3]"]
    set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[2]"]
    set_property PACKAGE_PIN "N2" [get_ports "DDR_DQS[2]"]
    set_property slew "FAST" [get_ports "DDR_DQS[2]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[2]"]
    set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[1]"]
    set_property PACKAGE_PIN "H2" [get_ports "DDR_DQS[1]"]
    set_property slew "FAST" [get_ports "DDR_DQS[1]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[1]"]
    set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[0]"]
    set_property PACKAGE_PIN "C2" [get_ports "DDR_DQS[0]"]
    set_property slew "FAST" [get_ports "DDR_DQS[0]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[0]"]
    set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[3]"]
    set_property PACKAGE_PIN "W2" [get_ports "DDR_DQS_n[3]"]
    set_property slew "FAST" [get_ports "DDR_DQS_n[3]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[3]"]
    set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[2]"]
    set_property PACKAGE_PIN "P2" [get_ports "DDR_DQS_n[2]"]
    set_property slew "FAST" [get_ports "DDR_DQS_n[2]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[2]"]
    set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[1]"]
    set_property PACKAGE_PIN "J2" [get_ports "DDR_DQS_n[1]"]
    set_property slew "FAST" [get_ports "DDR_DQS_n[1]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[1]"]
    set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[0]"]
    set_property PACKAGE_PIN "D2" [get_ports "DDR_DQS_n[0]"]
    set_property slew "FAST" [get_ports "DDR_DQS_n[0]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[0]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[9]"]
    set_property PACKAGE_PIN "G1" [get_ports "DDR_DQ[9]"]
    set_property slew "FAST" [get_ports "DDR_DQ[9]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[9]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[8]"]
    set_property PACKAGE_PIN "G2" [get_ports "DDR_DQ[8]"]
    set_property slew "FAST" [get_ports "DDR_DQ[8]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[8]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[7]"]
    set_property PACKAGE_PIN "F1" [get_ports "DDR_DQ[7]"]
    set_property slew "FAST" [get_ports "DDR_DQ[7]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[7]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[6]"]
    set_property PACKAGE_PIN "F2" [get_ports "DDR_DQ[6]"]
    set_property slew "FAST" [get_ports "DDR_DQ[6]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[6]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[5]"]
    set_property PACKAGE_PIN "E1" [get_ports "DDR_DQ[5]"]
    set_property slew "FAST" [get_ports "DDR_DQ[5]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[5]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[4]"]
    set_property PACKAGE_PIN "E3" [get_ports "DDR_DQ[4]"]
    set_property slew "FAST" [get_ports "DDR_DQ[4]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[4]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[3]"]
    set_property PACKAGE_PIN "D3" [get_ports "DDR_DQ[3]"]
    set_property slew "FAST" [get_ports "DDR_DQ[3]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[3]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[31]"]
    set_property PACKAGE_PIN "Y1" [get_ports "DDR_DQ[31]"]
    set_property slew "FAST" [get_ports "DDR_DQ[31]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[31]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[30]"]
    set_property PACKAGE_PIN "W3" [get_ports "DDR_DQ[30]"]
    set_property slew "FAST" [get_ports "DDR_DQ[30]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[30]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[2]"]
    set_property PACKAGE_PIN "B2" [get_ports "DDR_DQ[2]"]
    set_property slew "FAST" [get_ports "DDR_DQ[2]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[2]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[29]"]
    set_property PACKAGE_PIN "Y3" [get_ports "DDR_DQ[29]"]
    set_property slew "FAST" [get_ports "DDR_DQ[29]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[29]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[28]"]
    set_property PACKAGE_PIN "W1" [get_ports "DDR_DQ[28]"]
    set_property slew "FAST" [get_ports "DDR_DQ[28]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[28]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[27]"]
    set_property PACKAGE_PIN "U2" [get_ports "DDR_DQ[27]"]
    set_property slew "FAST" [get_ports "DDR_DQ[27]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[27]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[26]"]
    set_property PACKAGE_PIN "AA1" [get_ports "DDR_DQ[26]"]
    set_property slew "FAST" [get_ports "DDR_DQ[26]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[26]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[25]"]
    set_property PACKAGE_PIN "U1" [get_ports "DDR_DQ[25]"]
    set_property slew "FAST" [get_ports "DDR_DQ[25]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[25]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[24]"]
    set_property PACKAGE_PIN "AA3" [get_ports "DDR_DQ[24]"]
    set_property slew "FAST" [get_ports "DDR_DQ[24]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[24]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[23]"]
    set_property PACKAGE_PIN "R1" [get_ports "DDR_DQ[23]"]
    set_property slew "FAST" [get_ports "DDR_DQ[23]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[23]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[22]"]
    set_property PACKAGE_PIN "M2" [get_ports "DDR_DQ[22]"]
    set_property slew "FAST" [get_ports "DDR_DQ[22]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[22]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[21]"]
    set_property PACKAGE_PIN "T2" [get_ports "DDR_DQ[21]"]
    set_property slew "FAST" [get_ports "DDR_DQ[21]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[21]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[20]"]
    set_property PACKAGE_PIN "R3" [get_ports "DDR_DQ[20]"]
    set_property slew "FAST" [get_ports "DDR_DQ[20]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[20]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[1]"]
    set_property PACKAGE_PIN "C3" [get_ports "DDR_DQ[1]"]
    set_property slew "FAST" [get_ports "DDR_DQ[1]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[1]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[19]"]
    set_property PACKAGE_PIN "T1" [get_ports "DDR_DQ[19]"]
    set_property slew "FAST" [get_ports "DDR_DQ[19]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[19]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[18]"]
    set_property PACKAGE_PIN "N3" [get_ports "DDR_DQ[18]"]
    set_property slew "FAST" [get_ports "DDR_DQ[18]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[18]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[17]"]
    set_property PACKAGE_PIN "T3" [get_ports "DDR_DQ[17]"]
    set_property slew "FAST" [get_ports "DDR_DQ[17]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[17]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[16]"]
    set_property PACKAGE_PIN "M1" [get_ports "DDR_DQ[16]"]
    set_property slew "FAST" [get_ports "DDR_DQ[16]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[16]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[15]"]
    set_property PACKAGE_PIN "K3" [get_ports "DDR_DQ[15]"]
    set_property slew "FAST" [get_ports "DDR_DQ[15]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[15]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[14]"]
    set_property PACKAGE_PIN "J1" [get_ports "DDR_DQ[14]"]
    set_property slew "FAST" [get_ports "DDR_DQ[14]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[14]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[13]"]
    set_property PACKAGE_PIN "K1" [get_ports "DDR_DQ[13]"]
    set_property slew "FAST" [get_ports "DDR_DQ[13]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[13]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[12]"]
    set_property PACKAGE_PIN "L3" [get_ports "DDR_DQ[12]"]
    set_property slew "FAST" [get_ports "DDR_DQ[12]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[12]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[11]"]
    set_property PACKAGE_PIN "L2" [get_ports "DDR_DQ[11]"]
    set_property slew "FAST" [get_ports "DDR_DQ[11]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[11]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[10]"]
    set_property PACKAGE_PIN "L1" [get_ports "DDR_DQ[10]"]
    set_property slew "FAST" [get_ports "DDR_DQ[10]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[10]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[0]"]
    set_property PACKAGE_PIN "D1" [get_ports "DDR_DQ[0]"]
    set_property slew "FAST" [get_ports "DDR_DQ[0]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[0]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[3]"]
    set_property PACKAGE_PIN "AA2" [get_ports "DDR_DM[3]"]
    set_property slew "FAST" [get_ports "DDR_DM[3]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[3]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[2]"]
    set_property PACKAGE_PIN "P1" [get_ports "DDR_DM[2]"]
    set_property slew "FAST" [get_ports "DDR_DM[2]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[2]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[1]"]
    set_property PACKAGE_PIN "H3" [get_ports "DDR_DM[1]"]
    set_property slew "FAST" [get_ports "DDR_DM[1]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[1]"]
    set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[0]"]
    set_property PACKAGE_PIN "B1" [get_ports "DDR_DM[0]"]
    set_property slew "FAST" [get_ports "DDR_DM[0]"]
    set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[0]"]
    set_property iostandard "SSTL15" [get_ports "DDR_CS_n"]
    set_property PACKAGE_PIN "P6" [get_ports "DDR_CS_n"]
    set_property slew "SLOW" [get_ports "DDR_CS_n"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CS_n"]
    set_property iostandard "SSTL15" [get_ports "DDR_CKE"]
    set_property PACKAGE_PIN "V3" [get_ports "DDR_CKE"]
    set_property slew "SLOW" [get_ports "DDR_CKE"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CKE"]
    set_property iostandard "DIFF_SSTL15" [get_ports "DDR_Clk"]
    set_property PACKAGE_PIN "N4" [get_ports "DDR_Clk"]
    set_property slew "FAST" [get_ports "DDR_Clk"]
    set_property PIO_DIRECTION "INPUT" [get_ports "DDR_Clk"]
    set_property iostandard "DIFF_SSTL15" [get_ports "DDR_Clk_n"]
    set_property PACKAGE_PIN "N5" [get_ports "DDR_Clk_n"]
    set_property slew "FAST" [get_ports "DDR_Clk_n"]
    set_property PIO_DIRECTION "INPUT" [get_ports "DDR_Clk_n"]
    set_property iostandard "SSTL15" [get_ports "DDR_CAS_n"]
    set_property PACKAGE_PIN "P3" [get_ports "DDR_CAS_n"]
    set_property slew "SLOW" [get_ports "DDR_CAS_n"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CAS_n"]
    set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[2]"]
    set_property PACKAGE_PIN "M6" [get_ports "DDR_BankAddr[2]"]
    set_property slew "SLOW" [get_ports "DDR_BankAddr[2]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[2]"]
    set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[1]"]
    set_property PACKAGE_PIN "L6" [get_ports "DDR_BankAddr[1]"]
    set_property slew "SLOW" [get_ports "DDR_BankAddr[1]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[1]"]
    set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[0]"]
    set_property PACKAGE_PIN "L7" [get_ports "DDR_BankAddr[0]"]
    set_property slew "SLOW" [get_ports "DDR_BankAddr[0]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[0]"]
    set_property iostandard "SSTL15" [get_ports "DDR_Addr[9]"]
    set_property PACKAGE_PIN "H5" [get_ports "DDR_Addr[9]"]
    set_property slew "SLOW" [get_ports "DDR_Addr[9]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[9]"]
    set_property iostandard "SSTL15" [get_ports "DDR_Addr[8]"]
    set_property PACKAGE_PIN "J5" [get_ports "DDR_Addr[8]"]
    set_property slew "SLOW" [get_ports "DDR_Addr[8]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[8]"]
    set_property iostandard "SSTL15" [get_ports "DDR_Addr[7]"]
    set_property PACKAGE_PIN "J6" [get_ports "DDR_Addr[7]"]
    set_property slew "SLOW" [get_ports "DDR_Addr[7]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[7]"]
    set_property iostandard "SSTL15" [get_ports "DDR_Addr[6]"]
    set_property PACKAGE_PIN "J7" [get_ports "DDR_Addr[6]"]
    set_property slew "SLOW" [get_ports "DDR_Addr[6]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[6]"]
    set_property iostandard "SSTL15" [get_ports "DDR_Addr[5]"]
    set_property PACKAGE_PIN "K5" [get_ports "DDR_Addr[5]"]
    set_property slew "SLOW" [get_ports "DDR_Addr[5]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[5]"]
    set_property iostandard "SSTL15" [get_ports "DDR_Addr[4]"]
    set_property PACKAGE_PIN "K6" [get_ports "DDR_Addr[4]"]
    set_property slew "SLOW" [get_ports "DDR_Addr[4]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[4]"]
    set_property iostandard "SSTL15" [get_ports "DDR_Addr[3]"]
    set_property PACKAGE_PIN "L4" [get_ports "DDR_Addr[3]"]
    set_property slew "SLOW" [get_ports "DDR_Addr[3]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[3]"]
    set_property iostandard "SSTL15" [get_ports "DDR_Addr[2]"]
    set_property PACKAGE_PIN "K4" [get_ports "DDR_Addr[2]"]
    set_property slew "SLOW" [get_ports "DDR_Addr[2]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[2]"]
    set_property iostandard "SSTL15" [get_ports "DDR_Addr[1]"]
    set_property PACKAGE_PIN "M5" [get_ports "DDR_Addr[1]"]
    set_property slew "SLOW" [get_ports "DDR_Addr[1]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[1]"]
    set_property iostandard "SSTL15" [get_ports "DDR_Addr[14]"]
    set_property PACKAGE_PIN "G4" [get_ports "DDR_Addr[14]"]
    set_property slew "SLOW" [get_ports "DDR_Addr[14]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[14]"]
    set_property iostandard "SSTL15" [get_ports "DDR_Addr[13]"]
    set_property PACKAGE_PIN "F4" [get_ports "DDR_Addr[13]"]
    set_property slew "SLOW" [get_ports "DDR_Addr[13]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[13]"]
    set_property iostandard "SSTL15" [get_ports "DDR_Addr[12]"]
    set_property PACKAGE_PIN "H4" [get_ports "DDR_Addr[12]"]
    set_property slew "SLOW" [get_ports "DDR_Addr[12]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[12]"]
    set_property iostandard "SSTL15" [get_ports "DDR_Addr[11]"]
    set_property PACKAGE_PIN "G5" [get_ports "DDR_Addr[11]"]
    set_property slew "SLOW" [get_ports "DDR_Addr[11]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[11]"]
    set_property iostandard "SSTL15" [get_ports "DDR_Addr[10]"]
    set_property PACKAGE_PIN "J3" [get_ports "DDR_Addr[10]"]
    set_property slew "SLOW" [get_ports "DDR_Addr[10]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[10]"]
    set_property iostandard "SSTL15" [get_ports "DDR_Addr[0]"]
    set_property PACKAGE_PIN "M4" [get_ports "DDR_Addr[0]"]
    set_property slew "SLOW" [get_ports "DDR_Addr[0]"]
    set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[0]"]
    set_property iostandard "LVCMOS33" [get_ports "PS_PORB"]
    set_property PACKAGE_PIN "B5" [get_ports "PS_PORB"]
    set_property slew "slow" [get_ports "PS_PORB"]
    set_property drive "8" [get_ports "PS_PORB"]
    set_property iostandard "LVCMOS33" [get_ports "PS_SRSTB"]
    set_property PACKAGE_PIN "C9" [get_ports "PS_SRSTB"]
    set_property slew "slow" [get_ports "PS_SRSTB"]
    set_property drive "8" [get_ports "PS_SRSTB"]
    set_property iostandard "LVCMOS33" [get_ports "PS_CLK"]
    set_property PACKAGE_PIN "F7" [get_ports "PS_CLK"]
    set_property slew "slow" [get_ports "PS_CLK"]
    set_property drive "8" [get_ports "PS_CLK"]


    system_rst_clk_wiz_0_100M_0_board.xdc


    system_rst_clk_wiz_0_100M_0.xdc
    set_false_path -through [get_ports ext_reset_in]


    system_rst_clk_wiz_0_100M_0_ooc.xdc
    create_clock -name slowest_sync_clk -period 10 [get_ports slowest_sync_clk]


    system_rst_processing_system7_0_100M_1.xdc
    set_false_path -through [get_ports ext_reset_in]


    system_rst_processing_system7_0_100M_1_board.xdc


    system_rst_processing_system7_0_100M_1_ooc.xdc
    create_clock -name slowest_sync_clk -period 10 [get_ports slowest_sync_clk]


    system_auto_us_0_ooc.xdc
    create_clock -period 100.0 -name aclk [get_ports *_axi_aclk]


    system_auto_us_0_clocks.xdc


    system_clk_wiz_0_1.xdc
    create_clock -period 10.0 [get_ports clk_in1]
    set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.1


    system_clk_wiz_0_1_ooc.xdc


    system_clk_wiz_0_1_board.xdc


    system_xbar_0_ooc.xdc
    create_clock -period 100.0 -name aclk [get_ports aclk]


    system_auto_pc_1_ooc.xdc
    create_clock -period 100.0 -name aclk [get_ports aclk]


    system_auto_pc_0_ooc.xdc
    create_clock -period 100.0 -name aclk [get_ports aclk]


    system_v_tpg_0_1_ooc.xdc
    create_clock -name aclk -period 6.734 [get_ports aclk]
    create_clock -name s_axi_aclk -period 10 [get_ports s_axi_aclk]


    system_v_tpg_0_1_clocks.xdc
      set video_clk   [get_clocks -of [get_ports aclk]]
      set axilite_clk [get_clocks -of [get_ports s_axi_aclk]]
      set_max_delay -from $video_clk -to [get_cells -hierarchical -filter {NAME =~ *video_cntrl*/*SYNC2PROCCLK_I*/data_sync_reg[0]*}] -datapath_only [get_property -min PERIOD $video_clk]
      set_max_delay -from $axilite_clk -to [get_cells -hierarchical -filter {NAME =~ *video_cntrl*/*SYNC2VIDCLK_I*/data_sync_reg[0]*}] -datapath_only [get_property -min PERIOD $axilite_clk]

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