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AXI VDMA

Former Member

Hello,

I am having a problem with a simple design on the zedboard. My design consists of a Zynq processor, AXI VDMA, and a AXI TPG. The axi stream clock is set to run at 150Mhz (142.85Mhz actual). The problem is when I synthesize the design it fails timing. The AXI VDMA product guide PG020 shows that the Artix-7 family -1 speed grade can do 150 MHz AXI4-stream.

These are links of images for the timing report.
postimg.org/image/mx3xzenji
postimg.org/image/c206c42p3

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    Hi cuboard,

    I can't really do a detailed debug analysis of your design.  I would recommend that you take a look at some of the Vivado constraints training materials and training sessions on the Xilinx website.  I think that will help you the most.

    If you cannot get the Xilinx IP to license properly, you need to go to the Xilinx forums and get help from Xilinx.  Their system controls the licensing.  After you get the licensing straightened out, you will be able to run the example designs that I noted before.  That might be the most productive use of your time in getting a handle on why your design is not meeting timing.

    --Dan

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  • 0

    Hi cuboard,

    I can't really do a detailed debug analysis of your design.  I would recommend that you take a look at some of the Vivado constraints training materials and training sessions on the Xilinx website.  I think that will help you the most.

    If you cannot get the Xilinx IP to license properly, you need to go to the Xilinx forums and get help from Xilinx.  Their system controls the licensing.  After you get the licensing straightened out, you will be able to run the example designs that I noted before.  That might be the most productive use of your time in getting a handle on why your design is not meeting timing.

    --Dan

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