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AXI VDMA

Former Member

Hello,

I am having a problem with a simple design on the zedboard. My design consists of a Zynq processor, AXI VDMA, and a AXI TPG. The axi stream clock is set to run at 150Mhz (142.85Mhz actual). The problem is when I synthesize the design it fails timing. The AXI VDMA product guide PG020 shows that the Artix-7 family -1 speed grade can do 150 MHz AXI4-stream.

These are links of images for the timing report.
postimg.org/image/mx3xzenji
postimg.org/image/c206c42p3

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    Sorry for the delay,

    I posted a comment days ago but it still has not been added to this thread. Said waiting for admin confirmation I am guessing due to the length of the message.

    I have tried adding the Clocking Wizard IP core to the design which uses the MCMM to generate the 148.5MHz clock fro ma 100MHz clock. I still however get the failing timing problem. The problem happens when I connect the Test Pattern Generator to the VDMA IP Blocks. The design works fine at 100MHz at a low resolution. This is what caused me to try to increase the clock frequency as per the datasheet for the test pattern generator. It is asking for 148.5MHz at 1080p. The problem I encountered with 100MHz is the image that gets transferred into memory is alternating between a good frame and a corrupted frame.

    I have looked through the timing constraints on both the HDMI tutorial design as well as the FMC_IMAGEON design but the constraints look the same apart from pin assignments. I have a problem running the sample designs due to a problem with applying the license for the video evaluation, this prevents me from running the tutorials. It complains about the v_spec, v_cfa, ect cores.

    The constants that are automatically in the vivado project folder for this design ad linked below. I am not sure how what constraints must be applied to this design to make it work. If you could clarify the constraints it would be appropriated.

    pastebin.com/43BR59U7

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  • 0

    Sorry for the delay,

    I posted a comment days ago but it still has not been added to this thread. Said waiting for admin confirmation I am guessing due to the length of the message.

    I have tried adding the Clocking Wizard IP core to the design which uses the MCMM to generate the 148.5MHz clock fro ma 100MHz clock. I still however get the failing timing problem. The problem happens when I connect the Test Pattern Generator to the VDMA IP Blocks. The design works fine at 100MHz at a low resolution. This is what caused me to try to increase the clock frequency as per the datasheet for the test pattern generator. It is asking for 148.5MHz at 1080p. The problem I encountered with 100MHz is the image that gets transferred into memory is alternating between a good frame and a corrupted frame.

    I have looked through the timing constraints on both the HDMI tutorial design as well as the FMC_IMAGEON design but the constraints look the same apart from pin assignments. I have a problem running the sample designs due to a problem with applying the license for the video evaluation, this prevents me from running the tutorials. It complains about the v_spec, v_cfa, ect cores.

    The constants that are automatically in the vivado project folder for this design ad linked below. I am not sure how what constraints must be applied to this design to make it work. If you could clarify the constraints it would be appropriated.

    pastebin.com/43BR59U7

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