DDR Pins

Hi All,

I'm using Zed Board for my development activities. I'm using MIS/MIG for generating DDR3 SDRAM Controller. In the IO Planning Option while using Fixed Pin Out, I'm not able to specify the pin number / IO location as per schematic. Kindly do advice me on this issue.

0 Former Member over 13 years ago

MIS/MIG DDR3 generate netlist for programmable logic are. So this core can only use pins that are dedicated to PL.

Processor System 7 should contain nessesary DDR3 controller that can use current DDR3 implementation.
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0 Former Member over 13 years ago

georgedebel,

On the Zedboard all of the DDR3 is connected to the Processor System (PS). The MIS/MIG is expecting you to generate the interface to DDR3 via the Programmable Logic (PL) portion of Zynq. Since there is not DDR3 connected to the PL on the Zedboard, then you would not use the MIS/MIG to communicate to the DDR3.

Hope that explains things, let me know if it does not.
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0 Former Member over 13 years ago

thanks for information
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0 Former Member over 13 years ago in reply to Former Member

So you mean to say, one should add MPMC component in EDK. Using MPMC, one can interface with DDR3. am I right?
If yes then can you suggest document which shows how to do read/write operation? I need timing diagrams.
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