I started experimenting on the Zedboard recently. I want to implement a small design (as in, write VHDL code) which transmits a (hard coded for now) packet through the PHY layer (without using the PS). I don't need the receive part currently.
1)Is it possible to implement just the transmitter?
2)Also is it possible to do this purely from the PL layer (with VHDL code and constraint file), or is using the PS necessary?
I managed to switch values on 4 output pins at both rising and falling edges. (Don't know if it will violate any timing conditions at higher clock speeds).
In the Zedboard hardware user guide it is said that the TX clock is given by the PHY, so I thought i could just map my clock pin (input) there (right?).
And according to RGMII datasheet, I just need to transmit 11 or 00 on the TX_CTRL pin, to show if i am done transmitting or not.
But I don't see any pins for MDIO in the H/W user guide.
3)How do I configure the PHY then?
