I have do these Modification
1.set the 2 iic both emio
2.change the mem address 0x30000000 to 0x18000000
3.because the zedboard Y9 pin is not a lvds clock.
so I change it .
set_property PACKAGE_PIN Y9 [get_ports my_video_clk]
set_property IOSTANDARD LVCMOS25 [get_ports my_video_clk]
but implementation failed.
[Place 30-120] Sub-optimal placement for a BUFG-BUFG cascade pair. my_video_clk_IBUF_BUFG_inst, system_top_i/Video_Capture/VIDEO_MUX_0/U0/VIDEO_SEL_GEN[0].BUFGMUX_INST, fmc_imageon_hdmii_clk_IBUF_inst, system_top_i/Video_Capture/VIDEO_MUX_0/U0/VIDEO_SEL_GEN[0].BUFGMUX_INST, my_video_clk_IBUF_inst, and my_video_clk_IBUF_BUFG_inst
how can I fix this problem?
