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2nd Ethernet int to connect PS and PL vai GMII

Former Member

I redirected Ethernet 1 to PL according to this article http://zedboard.org/content/redirecting-peripherals-mio-emio

But I suppose it is not enough. It's necessary to modify Linux device tree and
1. add definition of the Ethernet 1 (it's simple)
2. tell Ethernet controller to get Rx/Tx clocks from EMIO - I do not have any idea how to do it.

Can you help with it?

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    The signals you redirected from Ethernet 1 to the PL are the interface from the MAC inside the Zynq Processor Section (PS) to a PHY that you will need to supply. Figure 16-8 in the Zynq-7000 AP SoC Technical Reference Manual (UG585) is a good illustraion.

     

    Just as the Ethernet 0 MAC on the ZedBoard is connected via the MIO pins to a Marvell PHY with an RGMII interface you will need to connect Ethernet 0 via the EMIO/Programmable Logic section via MII/GMII interface to an external PHY that you provide. On a ZedBoard that probably means adding an FMC daughter card with a PHY. Typically the board with the PHY will have an oscillator to generate clocks for the PHY which will in turn supply the required clocks to clock capable input pins on the Zynq programmable logic section. These are the signals you will connect to the Ethernet 1 MAC via EMIO.

     

    Here is an example of a ZedBoard compatible FMC PHY card: http://www.em.avnet.com/en-us/design/drc/Pages/ISM-Networking-FMC-Module.aspx

     

    -Gary

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    The signals you redirected from Ethernet 1 to the PL are the interface from the MAC inside the Zynq Processor Section (PS) to a PHY that you will need to supply. Figure 16-8 in the Zynq-7000 AP SoC Technical Reference Manual (UG585) is a good illustraion.

     

    Just as the Ethernet 0 MAC on the ZedBoard is connected via the MIO pins to a Marvell PHY with an RGMII interface you will need to connect Ethernet 0 via the EMIO/Programmable Logic section via MII/GMII interface to an external PHY that you provide. On a ZedBoard that probably means adding an FMC daughter card with a PHY. Typically the board with the PHY will have an oscillator to generate clocks for the PHY which will in turn supply the required clocks to clock capable input pins on the Zynq programmable logic section. These are the signals you will connect to the Ethernet 1 MAC via EMIO.

     

    Here is an example of a ZedBoard compatible FMC PHY card: http://www.em.avnet.com/en-us/design/drc/Pages/ISM-Networking-FMC-Module.aspx

     

    -Gary

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