2nd Ethernet int to connect PS and PL vai GMII

I redirected Ethernet 1 to PL according to this article http://zedboard.org/content/redirecting-peripherals-mio-emio

But I suppose it is not enough. It's necessary to modify Linux device tree and
1. add definition of the Ethernet 1 (it's simple)
2. tell Ethernet controller to get Rx/Tx clocks from EMIO - I do not have any idea how to do it.

Can you help with it?

0 Former Member over 11 years ago

The signals you redirected from Ethernet 1 to the PL are the interface from the MAC inside the Zynq Processor Section (PS) to a PHY that you will need to supply. Figure 16-8 in the Zynq-7000 AP SoC Technical Reference Manual (UG585) is a good illustraion.

Just as the Ethernet 0 MAC on the ZedBoard is connected via the MIO pins to a Marvell PHY with an RGMII interface you will need to connect Ethernet 0 via the EMIO/Programmable Logic section via MII/GMII interface to an external PHY that you provide. On a ZedBoard that probably means adding an FMC daughter card with a PHY. Typically the board with the PHY will have an oscillator to generate clocks for the PHY which will in turn supply the required clocks to clock capable input pins on the Zynq programmable logic section. These are the signals you will connect to the Ethernet 1 MAC via EMIO.

Here is an example of a ZedBoard compatible FMC PHY card: http://www.em.avnet.com/en-us/design/drc/Pages/ISM-Networking-FMC-Module.aspx

-Gary
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel
0 Former Member over 11 years ago

Hi Gary.
I wrote my IP core which resides in PL. IP core has GMII interface and can receive/send Ethernet frames. https://dl.dropboxusercontent.com/u/11851055/zedboard_2nd_eth.png
So I want to set up interface between my IP core and Ethernet 1 (PS).
I already redirected Data and CLK pins of Ethernet 1 to EMIO. Now I need to modify Linux device tree so Ethernet 1 gets Tx/Rx clocks from EMIO.
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel
0 Former Member over 11 years ago

Xilinx provides references how to use define clock sources in Device tree. But my knowledge is not enough to add necessary definitions.
https://github.com/Xilinx/linux-xlnx/blob/m...k/zynq-7000.txt
https://github.com/Xilinx/linux-xlnx/blob/m...fixed-clock.txt
https://github.com/Xilinx/linux-xlnx/blob/m...ck-bindings.txt

Much appreciate some help.
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel
0 Former Member over 11 years ago in reply to Former Member

The links in your post did not work for me so I am not sure what your references are.

But you should not need to define your GMII clock source in the device tree. If your IP is emulating the PHY interface to the Ethernet MAC GMII interface your IP just needs to provide the clock source that a PHY would normally provide.

-Gary
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel