Hi,
My application is about using the LVDS_25 feature for high speed communication (probably a SERDES or something else).
I use the PLLE2 primitive to synthesize a high frequency clock from the FCLK0 as an input clock.(or the clock conencted to Y9 which is 100Mhz). I saw that the capability of LVDS_25 pairs is about 950Mbps, but when i use PLLE2 to get an output differential clock of 400 Mhz, i see the amplitude is about 300mV for one end, and the receiver can not receive the data correctly. I know there is too much to talk about a perfect design to accomplish the LVDS_25 capabilities but, i want to learn the IC's capability in terms of its speed grade, to synthesize and transmit/receive these frequencies. I looked at nearly all the documentations but there is no statement like 'Zynq 7020 -1 speed grade PL side can transmit X Mhz'. I need this because i am designing a system which requires a high bandwidth and want to use the LVDS_25 pairs most efficiently (max frequency for each lane).
I accomplished to communicate in 350 Mhz, but higher than this, there exists corruption. (using 2 zedboards connected via cables - not FMC connectors together)
This is i think the most important feature of the PL side, and i will be pleased if someone has already has accomplished a data transfer in high speed and will publish some technical insight.
Regards,
Burak Metin
