I've gotten through a few of the tutorials. This has been challenging as there always seems to be some little thing that doesn't go correctly and I spend a bunch of time figuring out some obscure part of the toolset. It's very humbling. I'm not exactly proud of the time I've spent, but at least I've gotten somewhere. I haven't used the Xilinx toolset in a few years, which doesn't help.
I have a 32-address register bank defined and can access it via the SDK! Alright! I've edited the peripheral vhdl file (I call it bus_interface.vhd) and user_logic.vhd file and have created a third vhdl file with part of my logic. There are a bunch of other files that I need to add in later on after I've finished simulation. I'm using the peripheral file (bus_interface.vhd) as the top level file in my peripheral and have connected the sub-modules from within this file.
Now I'm stuck. I'm having difficulty figuring out:
1. How can I add in the new files (and in what tool)?
2. Are the files added into the library part or into the project?
3. How do I refresh the design so that the new files are actually integrated into the design?
4. How do I connect the device pins to the peripheral? (I think I just found a note that talks about this, but I thought I'd ask so that the response covers the full topic).
Thanks in advance!
