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SPI signals simulation

Former Member

Hello Everybody,

I am configuring actually the SPI in order to get data from my image sensor, But I want to know before i send it to my image sensor if there is an option to simulate the signals( SCLK,SI,CS_N), I want be sure that i m sending the good command and data.

Also i have a constraint between (CS_N ,SCLK) for example i have to wait 10 cycle of SCLK after CS_N is asserted and and 10 cycles of SCLK before Cs_N is deasserted, i had to respect a delay between adresse and data i have to wait 3 system of clock.
So my second question is how can I ensure those constraints.

this is my code for 4 registres i am using an axi spi:
#include "xspi.h"
#include "xparameters.h"
#include "xil_printf.h"
#include <stdio.h>
#include "sleep.h"



//XSpiPs spi; // instance of spi

static XSpi_Config *config;
static XSpi instance;


u8 spi_initialisation(u32 spi_device_ID, u32 slavemask)
{
tXSpi_Initialize(&instance,XPAR_PS7_SPI_0_DEVICE_ID);
tXSpi_SetOptions(&instance, 1);
tXSpi_SetSlaveSelectReg(&instance, 1);
tXSpi_Start(&instance);
tXSpi_IntrGlobalDisable(&instance);
treturn(XST_SUCCESS);
}



void spi_singlwrite(u8 adresse_0,u8 adresse_1,u8 data_0,u8 data_1)
{
tint status;
tusleep(10);
t            XSpi_Reset(&instance);
t            spi_initialisation(XPAR_PS7_SPI_0_DEVICE_ID,1);
ttttu8 byte_0 = adresse_0;
ttttu8 byte_1 = adresse_1;
ttttu8 byte_2 = data_0;
ttttu8 byte_3 = data_1;
ttttu8 writebuffer[4] = {byte_0,byte_1,byte_2,byte_3};
ttttXSpi_SetSlaveSelectReg(&instance, 1);
tt        status = XSpi_Transfer(&instance, writebuffer, NULL ,sizeof(writebuffer));
tt        XSpi_SetSlaveSelectReg(&instance, 0);


tt           if (status == XST_DEVICE_IS_STOPPED)
tt               txil_printf("XST_DEVICE_IS_STOPPED.r
");
tt           if (status == XST_DEVICE_BUSY)
tt                   txil_printf("XST_DEVICE_BUSY.r
");
tt           if (status == XST_SPI_NO_SLAVE)
tt                   txil_printf("XST_SPI_NO_SLAVE.r
");

}

int main(void)
{

  xil_printf("config spi start r
");
  spi_initialisation(XPAR_PS7_SPI_0_DEVICE_ID,0);

  spi_singlwrite(0x80,0x00,0x00,0x02);
  usleep(10);
  spi_singlwrite(0x80,0x01,0x00,0x90);
  usleep(10);
  spi_singlwrite(0x81,0x00,0x00,0x02);
  usleep(10);
  spi_singlwrite(0x81,0x01,0x00,0x90);
  xil_printf("config spi fin r
");
  return(0);
}
Thank you for your help.
Best regards,
Anisse BELMAJY

  • 0

    Hello Anisse,

     

    To check that you are sending good command and data on the SPI bus I would suggest executing your code and monitoring the SPI bus signals either externally with a logic analyzer or internally in the FPGA using the Vivado analyzer.

     

    As to the timing requirements on the SPI bus between CS_N, SCLK, and the address and data perhaps the provider of your image sensor has some example code or designs that implement these timings.

     

    Otherwise I do not know of any option within the AXI SPI core to program in these sort of delays. You could use the gross software delays you illustrate in the code snippet above or perhaps, depending on you SPI clock rate, you might be able to implement a more accurate delay using a timer or external clock counting circuit and an interrupt.

     

    Or you could consider implementing your own SPI controller in HDL that has the necessary delays built in.

     

    -Gary

  • 0

    Hello Gary,

    Thank you for your reply. I am trying to monitor my signals on ILA to get ensure that I am sending the right data.

    I hope that the provider has already implemented thoses timing restrictions. Because i am working with a camera HD and i m used to configure more than 200 registers.

    In HDL it will be quite hard to implement my own SPI for 235 registers.

    -Anisse