Hi people, I have a big question. Is it possible to use an external clock signal in the ZedBoard PL part? Thanks for your help!!!
Hi people, I have a big question. Is it possible to use an external clock signal in the ZedBoard PL part? Thanks for your help!!!
From the ZedBoard Hardware Users Guide:
2.5 Clock sources
The Zynq-7000 AP SoC’s PS subsystem uses a dedicated 33.3333 MHz clock source, IC18, Fox 767-33.333333-12, with series termination. The PS infrastructure can generate up to four PLL-based clocks for the PL system. An on-board 100 MHz oscillator, IC17, Fox 767-100-136, supplies the PL subsystem clock input on bank 13, pin Y9.
There are also two pairs of inputs from the FMC connector that are connected to clock capable inputs on the Zynq device:
FMC_CLK0_P / FMC-CLK0_N and FMC_CLK1_P / FMC-CLK1_N ( use the 'P' input for a single ended clock source)
And the JA PMOD connector has a pair of pins (JA4 and JA10) that are connected to clock capable inputs.
-Gary
From the ZedBoard Hardware Users Guide:
2.5 Clock sources
The Zynq-7000 AP SoC’s PS subsystem uses a dedicated 33.3333 MHz clock source, IC18, Fox 767-33.333333-12, with series termination. The PS infrastructure can generate up to four PLL-based clocks for the PL system. An on-board 100 MHz oscillator, IC17, Fox 767-100-136, supplies the PL subsystem clock input on bank 13, pin Y9.
There are also two pairs of inputs from the FMC connector that are connected to clock capable inputs on the Zynq device:
FMC_CLK0_P / FMC-CLK0_N and FMC_CLK1_P / FMC-CLK1_N ( use the 'P' input for a single ended clock source)
And the JA PMOD connector has a pair of pins (JA4 and JA10) that are connected to clock capable inputs.
-Gary
great! thank you very much for your help!