Use an external clock signal on the zedboard

Hi people, I have a big question. Is it possible to use an external clock signal in the ZedBoard PL part? Thanks for your help!!!

0 Former Member over 11 years ago

From the ZedBoard Hardware Users Guide:

2.5 Clock sources
The Zynq-7000 AP SoC’s PS subsystem uses a dedicated 33.3333 MHz clock source, IC18, Fox 767-33.333333-12, with series termination. The PS infrastructure can generate up to four PLL-based clocks for the PL system. An on-board 100 MHz oscillator, IC17, Fox 767-100-136, supplies the PL subsystem clock input on bank 13, pin Y9.

There are also two pairs of inputs from the FMC connector that are connected to clock capable inputs on the Zynq device:
FMC_CLK0_P / FMC-CLK0_N and FMC_CLK1_P / FMC-CLK1_N ( use the 'P' input for a single ended clock source)

And the JA PMOD connector has a pair of pins (JA4 and JA10) that are connected to clock capable inputs.

-Gary
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0 Former Member over 11 years ago in reply to Former Member

great! thank you very much for your help!
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0 ashahsana over 11 years ago

Hello everyone
I want to receive clock from FMC_CLK0_P / FMC-CLK0_N and FMC_CLK1_P / FMC-CLK1_N of 7z020 for my mezzanine card.
Can anyone explain how is it possible.
thanks in advance
Sana
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0 Former Member over 11 years ago in reply to ashahsana

As discussed in your other post, you will need to look at the documentation for the ZC702 board to determine the pin assignments and constraints needed to match the Xilinx ZC702 board.



The Xilinx ZC702 board is supported on the Xilinx community forums: http://forums.xilinx.com/ but here are a couple of places to start:
     http://www.xilinx.com/support/documentation/boards_and_kits/zc702_zvik/ug850-zc702-eval-bd.pdf

     http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/boards_and_kits/zynq-7000_soc_boards_and_kits/zynq-7000_soc_zc702_evaluation_kit.html

     -Gary
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