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Problem about Axi4-Stream and VDMA

Former Member

   I have a simple design in which i want to transfer the video data to DDR memory using VDMA IP.  Since the video source has a XSVI interface but VDMA need an AXI-Stream interface, so i use a Video In to AXI4-Stream IP(I call it vid_in_axi4s) to connect them.  But there is no data in memory.  So i use chipscope to debug it.    First, i add an Integrated Logic Analyzer between the video source and the vid_in_axi4s,  and i can see the data flow in chipscope analyzeru3002 Second,  i add a chipscope axi monitor IP between vid_in_axi4s and VDMA,  but there is no data showing in analyzeru3002So i can make a conclusion that the problem is between vid_in_axi4s and VDMAu3002

    To debug the problem, i modified my designu3002 I  remove the other IPs except the video source  and  vid_in_axi4su3002 I make the vid_in_axi4s::M_AXIS_VDIEO ports External  and  Loc the tdata pin  in  LED IOB,  tready pin in one Button in UCF fileu3002 Only  when  i  pressed  the Button(tready pin location),  i  can  see the LED onu3002 

     So,  i  think  my problem is caused by the  AXI4-Stream interface ( the tready signal) u3002 It seems that  i need  to trigger  the vid_in_axi4s::M_AXIS_VIDEO::tready signal u3002 I  really have done some basic configuration about  the VDMAu3002 How can i solve this problem?!   Is the job of triggering the vid_in_axi4s::M_AXIS_VIDEO::tready signal  done by VDMA?!

  • 0

    BEGIN v_vid_in_axi4s
    PARAMETER INSTANCE = v_vid_in_axi4s_0
    PARAMETER HW_VER = 2.01.a
    PARAMETER C_M_AXIS_VIDEO_DATA_WIDTH = 8
    PARAMETER C_M_AXIS_VIDEO_FORMAT = 2
    BUS_INTERFACE M_AXIS_VIDEO = v_vid_in_axi4s_0_M_AXIS_VIDEO
    PORT aclk = clk_150mhz
    PORT vid_de = axi_tpg_0_active_video
    PORT vid_vblank = axi_tpg_0_vblank
    PORT vid_hblank = axi_tpg_0_hblank
    PORT vid_vsync = axi_tpg_0_vsync
    PORT vid_hsync = axi_tpg_0_hsync
    PORT vid_data = 0x00 & axi_tpg_0_video_data
    PORT aclken = net_vcc
    PORT axis_enable = net_vcc
    PORT rst = proc_sys_reset_1_BUS_STRUCT_RESET
    PORT aresetn = TPG_RST_O
    PORT m_axis_video_tdata = v_vid_in_m_axis_tdata
    PORT vid_in_clk = clk148mhz
    END

    BEGIN axi_vdma
    PARAMETER INSTANCE = axi_vdma_0
    PARAMETER HW_VER = 5.03.a
    PARAMETER C_USE_FSYNC = 1
    PARAMETER C_INCLUDE_S2MM = 1
    PARAMETER C_M_AXI_MM2S_DATA_WIDTH = 64
    PARAMETER C_M_AXIS_MM2S_TDATA_WIDTH = 64
    PARAMETER C_MM2S_LINEBUFFER_THRESH = 8
    PARAMETER C_PRMRY_IS_ACLK_ASYNC = 1
    PARAMETER C_M_AXI_S2MM_DATA_WIDTH = 64
    PARAMETER C_INCLUDE_S2MM_DRE = 1
    PARAMETER C_S2MM_LINEBUFFER_DEPTH = 4096
    PARAMETER C_S2MM_SOF_ENABLE = 0
    PARAMETER C_INTERCONNECT_M_AXI_S2MM_AW_REGISTER = 8
    PARAMETER C_INTERCONNECT_M_AXI_S2MM_AR_REGISTER = 8
    PARAMETER C_INTERCONNECT_M_AXI_S2MM_W_REGISTER = 8
    PARAMETER C_INTERCONNECT_M_AXI_S2MM_R_REGISTER = 8
    PARAMETER C_INTERCONNECT_M_AXI_S2MM_B_REGISTER = 8
    PARAMETER C_INTERCONNECT_M_AXI_S2MM_WRITE_FIFO_DEPTH = 512
    PARAMETER C_INTERCONNECT_M_AXI_S2MM_WRITE_ISSUING = 8
    PARAMETER C_INTERCONNECT_S_AXI_LITE_AW_REGISTER = 8
    PARAMETER C_INTERCONNECT_S_AXI_LITE_AR_REGISTER = 8
    PARAMETER C_INTERCONNECT_S_AXI_LITE_W_REGISTER = 8
    PARAMETER C_INTERCONNECT_S_AXI_LITE_R_REGISTER = 8
    PARAMETER C_INTERCONNECT_S_AXI_LITE_B_REGISTER = 8
    PARAMETER C_BASEADDR = 0x43000000
    PARAMETER C_HIGHADDR = 0x4300ffff
    PARAMETER C_INTERCONNECT_M_AXI_S2MM_WRITE_FIFO_DELAY = 1
    BUS_INTERFACE S_AXI_LITE = axi_lite
    BUS_INTERFACE M_AXI_MM2S = axi_inout
    BUS_INTERFACE M_AXIS_MM2S = axi_vdma_0_M_AXIS_MM2S
    BUS_INTERFACE S_AXIS_S2MM = v_vid_in_axi4s_0_M_AXIS_VIDEO
    BUS_INTERFACE M_AXI_S2MM = axi_inout
    PORT s_axis_s2mm_tdata = 0x00 & v_vid_in_m_axis_tdata
    PORT m_axis_mm2s_aclk = clk_150mhz
    PORT mm2s_buffer_almost_empty = axi_vdma_0_mm2s_buffer_almost_empty
    PORT mm2s_buffer_empty = axi_vdma_0_mm2s_buffer_empty
    PORT s_axi_lite_aclk = clk_75mhz
    PORT m_axi_mm2s_aclk = clk_150mhz
    PORT mm2s_introut = axi_vdma_0_mm2s_introut
    PORT s_axis_s2mm_aclk = clk_150mhz
    PORT m_axi_s2mm_aclk = clk_150mhz
    PORT s2mm_fsync_out = axi_vdma_0_s2mm_fsync_out
    END

    Any suggestion would be appreciate!
    Dec

  • 0

    If you're using the Video In to AXI4-Stream IP, there's a signal called axis_enable. In the tutorials, there's always a Video Timing Controller IP. It drives axis_enable to synchronize with the start of the new frame. When this signal is low, no data is written to memory. If you don't have a VTC, have your logic assert this signal high to enable the stream interface.

  • 0

    Yes you need to drive the fsync-signal for at least a clock cycle.
    When VDMA receives fsync, then tready gets asserted.

    Note that Xilinx has a working xsvi2axi core:
    http://www.xilinx.com/support/documentation/application_notes/xapp521_XSVI_AXI4.pdf