Actions
Forum Thread Details
  • State Not Answered
  • Replies 8 replies
  • Subscribers 345 subscribers
  • Views 1250 views
  • Users 0 members are here
Related

PL Clock Reconfiguration

Former Member

Hi!

For a design I am working on, after synthesis, a clock of 250Mhz seemed to be okay. For this reason I configured FCLK_CLK0 to generate a clock with this frequency using XPS.

After implementation, the maximum clock shrunk to about 125Mhz (and the design indeed does not work ;) ), because the design is quite big and I'm getting much routing overhead.

For the same reason, implementation took ~10hours.

Is there a way to reconfigure FCLK_CLK0 without running implementation again?

Thx in advance!

  • 0

    I'm confused regarding what you are saying.  If you configure FCLK_CLK0 to be 250 MHz in the PS Configuration tool, and you verify that the Actual frequency matches the Requested, then you should get 250 MHz on FCLK_CLK0.  If you don't meet timing in the PL with FCLK_CLK0 = 250 MHz, that is a completely separate issue related to closing timing in fabric.

     

    Regarding your specific question, it is possible to change the frequency of FCLK_CLK0 on the fly in software by changing the PLL registers.  However, I'm not sure I would recommend this.

     

    Bryan

  • 0 in reply to bhfletcher

    Hi!

    I don't meet timing in the PL with FCLK_CLK0 = 250MHz although synthesis told me I would. After routing I know that I could use FCLK_CLK0 = 100MHz. So I'd like to set the clock to that value so that I am able to test whether the design would work in principle at least.

    The only way how I know to do this is changing the clock in XPS and running synthesis and implementation again, making my PC sort of useless for that time.

    So having the option to just change some registers in Software would be a good option for testing purpose at least.

    Is it correct that this is done in 'ps7_init.tcl' which is exported to the SDK? Where can I get more info on this? ('ps7_pll_init_data' and 'ps7_clock_init_data'?)

    And most important: Which is the reason for not recommending this?

    Thanks for your help!

  • 0 in reply to Former Member

    VoSte,

    You are correct that information is configured within the ps7_init.tcl file, and more accurately within the ps7_init.c file within SDK.

    You could get yourself into a state where the PS's PLL's can't gain lock again after the frequency change, so changing it on the fly is not recommended.  If you do, however, want to change this after your design is already compiled down instead of changing it after the PS is already loaded, then you could do this by modifying the values within the ps7_init.c file.

    You may want to take a look at this file:

    <project_dir>/<project_name>.sdk/SDK/SDK_Export/hw/ps7_init.html

    It has a nice outline of what all of the configuration registers are set to.  Let me know if this helps.

  • 0 in reply to Former Member

    Thank you very much!

    I must have been blind to not have seen this file... ;)

    This helped alot!

  • 0 in reply to Former Member

    Great!  Let us know if you're successful, and how you did it - that way the community can benefit from your work!

  • 0

    Hi!

    For my design, I've also changed the FCLK_CLK0 clock frequency in XPS, on Zynq tab, to 25 MHz (from default 100 MHz).
    I'd like to use it to generate vga sync signals, but the used monitor displays an error message with the measured frequencies.

    According to the desired display mode parameters, the realized sync signals are generated from 100 MHz FCLK_CLK0 clock  instead of the previously set 25 MHz.

    Already tried to clear the whole design, but didn't help.

    Someone's got an idea, where should I look for possible design errors?

    Thanks!

  • 0 in reply to Former Member

    I've changed one of my system's clock frequency (FCLK_CLK3) from 25 to 1 MHz. When I run a standalone application I can check that the new frequency was set using Chipscope, but when I generate an FSBL and a BOOT image to run Linux I still get the 25 MHz on Chipscope using a Linux Application. Any hints?

  • 0 in reply to Former Member

    Found that linux changes PL on boot.
    To confirm the issue I made the FPGAx_CLK's external and interrupted the boot of u-boot. My Logicanalyser shows the Values specified in XPS
    After resuming the boot, Linux changes the clock. This can also be seen in the values of /sys/kernel/debug/clk/ps_clk/iopll/FPGAx_CLK/clk_rate which are different than the ones specified in XPS.
    Does anybody know where Linux takes these values from, devicetree?