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PL Clock Reconfiguration

Former Member

Hi!

For a design I am working on, after synthesis, a clock of 250Mhz seemed to be okay. For this reason I configured FCLK_CLK0 to generate a clock with this frequency using XPS.

After implementation, the maximum clock shrunk to about 125Mhz (and the design indeed does not work ;) ), because the design is quite big and I'm getting much routing overhead.

For the same reason, implementation took ~10hours.

Is there a way to reconfigure FCLK_CLK0 without running implementation again?

Thx in advance!

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  • 0

    Hi!

    For my design, I've also changed the FCLK_CLK0 clock frequency in XPS, on Zynq tab, to 25 MHz (from default 100 MHz).
    I'd like to use it to generate vga sync signals, but the used monitor displays an error message with the measured frequencies.

    According to the desired display mode parameters, the realized sync signals are generated from 100 MHz FCLK_CLK0 clock  instead of the previously set 25 MHz.

    Already tried to clear the whole design, but didn't help.

    Someone's got an idea, where should I look for possible design errors?

    Thanks!

  • 0 in reply to Former Member

    I've changed one of my system's clock frequency (FCLK_CLK3) from 25 to 1 MHz. When I run a standalone application I can check that the new frequency was set using Chipscope, but when I generate an FSBL and a BOOT image to run Linux I still get the 25 MHz on Chipscope using a Linux Application. Any hints?

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  • 0 in reply to Former Member

    Found that linux changes PL on boot.
    To confirm the issue I made the FPGAx_CLK's external and interrupted the boot of u-boot. My Logicanalyser shows the Values specified in XPS
    After resuming the boot, Linux changes the clock. This can also be seen in the values of /sys/kernel/debug/clk/ps_clk/iopll/FPGAx_CLK/clk_rate which are different than the ones specified in XPS.
    Does anybody know where Linux takes these values from, devicetree?