Hey Guys,
we are working on a custom Board design related to the ZedBoard. The length of data line etc. are different to the zedboard design and therefore i thought we need to change the delays/tracelength in zynq hardware design (http://www.xilinx.com/support/answers/46778.html). Since we have some other issues, we cannot configure the hardware design due to the FTDI FT232H Controller, which we are using and seems not to be configured for JTAG.
Anyway, to analyze how the impact of changing the delays in hardware design is, we set all delays for the zedboard reference design to zero and generated the outpout again to programm the zedboard zynq PS.
After building the design and configured the PS, we started an simple hello world application without any error. Moreover we startet the DRAM test and Memory Test application from SDK to see how the delay change will impact the zedboard ddr config.
The weird thing is, that nothing seems to be gone bad. All test were passed and there seems no real impact of changing the delays/trancelength for the zedboard design.
How is this even possible?? (DRAM Training were enabled)
Thanks and regards
Jan