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Zedboard DDR3 Controller Configuration

Former Member

Hey Guys,

we are working on a custom Board design related to the ZedBoard. The length of data line etc. are different to the zedboard design and therefore i thought we need to change the delays/tracelength in zynq hardware design (http://www.xilinx.com/support/answers/46778.html). Since we have some other issues, we cannot configure the hardware design due to the FTDI FT232H Controller, which we are using and seems not to be configured for JTAG.

Anyway, to analyze how the impact of changing the delays in hardware design is, we set all delays for the zedboard reference design to zero and generated the outpout again to programm the zedboard zynq PS.

After building the design and configured the PS, we started an simple hello world application without any error. Moreover we startet the DRAM test and Memory Test application from SDK to see how the delay change will impact the zedboard ddr config.

The weird thing is, that nothing seems to be gone bad. All test were passed and there seems no real impact of changing the delays/trancelength for the zedboard design.

How is this even possible?? (DRAM Training were enabled)

Thanks and regards
Jan

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    On the positive side, I'm very happy to hear your DDR3 is working!

     

    In terms of trace length matching, there was an update published back in September 2015 to UG933 that added a lot of flexibility to the matching tolerance. If you are using a 1600 device but only running at 1066 or 800, you will find that you have >10x the tolerance allowed. See Appendix A here:

    http://www.xilinx.com/support/documentation/user_guides/ug933-Zynq-7000-PCB.pdf

     

    Regarding what you enter into the tools, that is also pretty resilient for DDR3. Zynq goes through a tuning process to optimize the read/write windows for the DDR3 on startup, so having the exact numbers aren't critical. Being inside the valid window is preferred.

     

    In SDK, you can also try the Zynq DRAM Diagnostics Test to investigate where your valid windows are.

     

    Bryan

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  • 0

    On the positive side, I'm very happy to hear your DDR3 is working!

     

    In terms of trace length matching, there was an update published back in September 2015 to UG933 that added a lot of flexibility to the matching tolerance. If you are using a 1600 device but only running at 1066 or 800, you will find that you have >10x the tolerance allowed. See Appendix A here:

    http://www.xilinx.com/support/documentation/user_guides/ug933-Zynq-7000-PCB.pdf

     

    Regarding what you enter into the tools, that is also pretty resilient for DDR3. Zynq goes through a tuning process to optimize the read/write windows for the DDR3 on startup, so having the exact numbers aren't critical. Being inside the valid window is preferred.

     

    In SDK, you can also try the Zynq DRAM Diagnostics Test to investigate where your valid windows are.

     

    Bryan

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