Greetings everyone,
I'm working on a project with a ZedBoard, and I'm having a little trouble. I'm primarily an embedded ARM developer, and I'm pretty to new Xilinx tools - and completely new to Vivado. This is my first time using Zynq.
I've created a Block design that includes two AXI_Uart16550 cores and a clock wizard (the final design will include more uarts, but I'd like to get it working with two). I need a very strange baud rate, which is the reason for the clock wiz. During synthesis and implementation, I'm seeing some clocking failures and although I can produce a bitstream, things aren't working as I would expect.
Can anyone have a look at my vivado project and see if I've done something incorrectly? I think I might have the processor resets wrong, but I'm not at all sure.
Any help would be greatly appreciated!
Vivado 2015.4 Project
https://file.io/d6cweS
James
