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Vivado Help on Zed

Former Member

Greetings everyone,

I'm working on a project with a ZedBoard, and I'm having a little trouble.  I'm primarily an embedded ARM developer, and I'm pretty to new Xilinx tools - and completely new to Vivado.  This is my first time using Zynq.

I've created a Block design that includes two AXI_Uart16550 cores and a clock wizard (the final design will include more uarts, but I'd like to get it working with two).  I need a very strange baud rate, which is the reason for the clock wiz.  During synthesis and implementation, I'm seeing some clocking failures and although I can produce a bitstream, things aren't working as I would expect.

Can anyone have a look at my vivado project and see if I've done something incorrectly?  I think I might have the processor resets wrong, but I'm not at all sure.

Any help would be greatly appreciated!

Vivado 2015.4 Project
https://file.io/d6cweS

James

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    Gary,

    That's strange.  It was working when I posted this.  Here's a new link: https://file.io/iNcEfp

    I appreciate you taking the time to respond.  That's pretty much what I did, but connection automation seemed to have a little trouble because of the clocking wizard in the mix.

    I just can't figure out why its failing some clocking - the design isn't super high speed (Clocking wizard of 49.152Mhz) and isn't very complex (low resource utilization).

    If you can get the file and provide any insight, I'd sure apprecaite it.

    James

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    Gary,

    That's strange.  It was working when I posted this.  Here's a new link: https://file.io/iNcEfp

    I appreciate you taking the time to respond.  That's pretty much what I did, but connection automation seemed to have a little trouble because of the clocking wizard in the mix.

    I just can't figure out why its failing some clocking - the design isn't super high speed (Clocking wizard of 49.152Mhz) and isn't very complex (low resource utilization).

    If you can get the file and provide any insight, I'd sure apprecaite it.

    James

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