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Vivado Help on Zed

Former Member

Greetings everyone,

I'm working on a project with a ZedBoard, and I'm having a little trouble.  I'm primarily an embedded ARM developer, and I'm pretty to new Xilinx tools - and completely new to Vivado.  This is my first time using Zynq.

I've created a Block design that includes two AXI_Uart16550 cores and a clock wizard (the final design will include more uarts, but I'd like to get it working with two).  I need a very strange baud rate, which is the reason for the clock wiz.  During synthesis and implementation, I'm seeing some clocking failures and although I can produce a bitstream, things aren't working as I would expect.

Can anyone have a look at my vivado project and see if I've done something incorrectly?  I think I might have the processor resets wrong, but I'm not at all sure.

Any help would be greatly appreciated!

Vivado 2015.4 Project
https://file.io/d6cweS

James

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    Hello James,

     

    I took a quick look at your block design. It looks like you are clocking the AXI interface with the output of your clock wizard. Not sure why you would want to do that. If all you want is a custom baud rate the simplest thing to do would be to configure the axi_uart16650 IP to use an external clock and let the axi interfaces clock as usual with the fclk_clk0 outputs.

     

    You may not even need a clock wizard. Depending on your frequency requirements (input clock does need to be 1/2 axi clock or less)  you might be able to just enable one of the other PL fabric clocks (FCLK_CLKK1) to the input required for the baud rate generator and use that output. To do this you would re-customized the Zynq PS block, select Clock Configuration and enable and set a second PL Fabric Clock.

     

    -Gary

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  • 0

    Hello James,

     

    I took a quick look at your block design. It looks like you are clocking the AXI interface with the output of your clock wizard. Not sure why you would want to do that. If all you want is a custom baud rate the simplest thing to do would be to configure the axi_uart16650 IP to use an external clock and let the axi interfaces clock as usual with the fclk_clk0 outputs.

     

    You may not even need a clock wizard. Depending on your frequency requirements (input clock does need to be 1/2 axi clock or less)  you might be able to just enable one of the other PL fabric clocks (FCLK_CLKK1) to the input required for the baud rate generator and use that output. To do this you would re-customized the Zynq PS block, select Clock Configuration and enable and set a second PL Fabric Clock.

     

    -Gary

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