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HDMI display controler

Former Member

Hi everybody,

I'm lost with vivado versions, i have done the tutto of " diplay controler HDMI" on version 2014.1 i have got my color bars in my monitor via HDMI till now all it's good.
But when i got copy this project to another machine version 2015.3, i have upgrade all ips after synthetising, implementation and bitstream.

I have run my software in SDK as i have done in version 2014.1. But the prob i cannot see the color bars.
My monitor does'nt recongnize the HDMI :(.

My question is : does someone know the reason why i cannot see the same results ??
Do I need to change something to make my porject 2015.3 works as 2014.1 ?.

Thank your for your feedbacks.

Kind regards

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    The HDMI reference design is routed with Vivado 2016.3. As far as I can see on the ILA. I have the v_sync, h_sync and video data outputs out of the video stream to video output block, but one issue is that the signals I'm observing on the ILA are not coming out of the FPGA. Mainly out of the OBUFT drivers. I checked the 3-State enable on the OBUFT and it is low, which is correct for active low. I checked the constraints and the hdmio_hsync is on V17, and hdmio_io_vsynci s on W17 I/O pads, which is what it supposed to be on the Zedboard Rev D2. Any suggestions on why the hdmio signals are not being driven out of the FPGA?

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    The HDMI reference design is routed with Vivado 2016.3. As far as I can see on the ILA. I have the v_sync, h_sync and video data outputs out of the video stream to video output block, but one issue is that the signals I'm observing on the ILA are not coming out of the FPGA. Mainly out of the OBUFT drivers. I checked the 3-State enable on the OBUFT and it is low, which is correct for active low. I checked the constraints and the hdmio_hsync is on V17, and hdmio_io_vsynci s on W17 I/O pads, which is what it supposed to be on the Zedboard Rev D2. Any suggestions on why the hdmio signals are not being driven out of the FPGA?

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