I am currently trying to implement an ethernet driven algorithm in the Zedboard. The board will interface with a GigE Vision Camera and I want to pull Ethernet packets directly into the Programmable Logic.
I understand that you need an external PHY that you provide ( I have one ordered). I am not fully understanding how to utilize the "GMII to RGMII v3.0" IP Core that Xilinx provides. I am not sure where that is sending the information.
It gives a gmii interface to the EMIO, but where do I access that data? I'm using Vivado 2014.2 and using the block design I can't see where the data will be accessed from the PS. When you switch the Eth1 peripheral to EMIO, it creates a GMII port in the processing system. This connects to the GMII port of the IP core.
Do you connect whatever customized IP you create to that same connection? Any information on how to correctly use this IP would be great.
