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How can I access block ram on both PS and PL when I use ZedBoard?

Former Member

Hello everybody~

Now I have a question. I need archive this:
1. send data from PS to bram in PL by AXI.
2. read bram in PL.

For first task, I think I can use axi-bram-controller to transfer data. But for second task, I don't know how to access the bram in PL. Do I need design my own bram controller and use it to access the same bram, or just modify the axi-bram-controller to add my own code?

Thanks~~ :D

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  • 0

    Hello Marina,

     

    This interface should be pretty straightforward. Just implement an AXI BRAM controller connected to one port of a Dual Port BRAM. Connect your PL (Programmable Logic) design to the other port of the Dual Port BRAM. Reading from the Dual Port BRAM via the AXI BRAM controller should not alter the contents of the BRAM.

     

    I would suggest looking at the addressing and the data width of your AXI interface to the BRAM. And make sure that your PL design is not causing the issue. Take a second look at your software to make sure you are only performing reads.

     

    -Gary

  • 0 in reply to Former Member

    Thank you for the replay. I recently discovered that I had a bad management of the write enable array of the bram. So I am actually able to read what the axi is writing on the bram, using my block of vhdl.
    Unfortunately another problem occurred. Now my axi seems not to be able to read what has been written by the vhdl block, but is totaly capable to read what he wrote before.
    Should I look to my enable signals and stuff in the vhdl or might this be related to memory caching and so on? (somebody pointed that out online but I am pretty confused)
    I am using the mmap function to access the memory space.
    Thanks for your help and any advice anybody would be able to provide

    Marina

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  • 0 in reply to Former Member

    Thank you for the replay. I recently discovered that I had a bad management of the write enable array of the bram. So I am actually able to read what the axi is writing on the bram, using my block of vhdl.
    Unfortunately another problem occurred. Now my axi seems not to be able to read what has been written by the vhdl block, but is totaly capable to read what he wrote before.
    Should I look to my enable signals and stuff in the vhdl or might this be related to memory caching and so on? (somebody pointed that out online but I am pretty confused)
    I am using the mmap function to access the memory space.
    Thanks for your help and any advice anybody would be able to provide

    Marina

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