I have a design running on the Zedboard. It is based on the FMC- IMAGEON Vita Pass through tutorial. I have taken this design and modified it. I want to further modify it by adding a VDMA so that I can cope with different resolutions and frame rates.I am following the design guide lines in the LogiCORE IP Video In to AXI4-Stream v3.0 and the AXI Video Direct Memory Access v6.1. I have added the VDMA to the design and I get the following errors:
ERROR: [BD 41-237] Bus Interface property FREQ_HZ does not match between /processing_system7_0_axi_periph/s01_couplers/auto_pc/S_AXI(100000000) and /axi_vdma_0/M_AXI_MM2S(142857132)
ERROR: [BD 41-237] Bus Interface property CLK_DOMAIN does not match between /processing_system7_0_axi_periph/s01_couplers/auto_pc/S_AXI(zed_hdmi_processing_system7_0_0_FCLK_CLK0) and /axi_vdma_0/M_AXI_MM2S(zed_hdmi_processing_system7_0_0_FCLK_CLK1)
CRITICAL WARNING: [BD 41-237] Bus Interface property TDATA_NUM_BYTES does not match between /fmc_imageon_hdmio_rgb/v_rgb2ycrcb_0/video_in(3) and /axi_vdma_0/M_AXIS_MM2S(4)
ERROR: [BD 41-237] Bus Interface property FREQ_HZ does not match between /axi_vdma_0/S_AXIS_S2MM(100000000) and /fmc_imageon_vita_color/v_cfa_0/video_out(142857132)
ERROR: [BD 41-237] Bus Interface property CLK_DOMAIN does not match between /axi_vdma_0/S_AXIS_S2MM(zed_hdmi_processing_system7_0_0_FCLK_CLK0) and /fmc_imageon_vita_color/v_cfa_0/video_out(zed_hdmi_processing_system7_0_0_FCLK_CLK1)
Are there any good examples that will show me how to connect up the VDMA?
