Adding a VDMA to a design

I have a design running on the Zedboard. It is based on the FMC- IMAGEON Vita Pass through tutorial. I have taken this design and modified it. I want to further modify it by adding a VDMA so that I can cope with different resolutions and frame rates.I am following the design guide lines in the LogiCORE IP Video In to AXI4-Stream v3.0 and the AXI Video Direct Memory Access v6.1. I have added the VDMA to the design and I get the following errors:

ERROR: [BD 41-237] Bus Interface property FREQ_HZ does not match between /processing_system7_0_axi_periph/s01_couplers/auto_pc/S_AXI(100000000) and /axi_vdma_0/M_AXI_MM2S(142857132)

ERROR: [BD 41-237] Bus Interface property CLK_DOMAIN does not match between /processing_system7_0_axi_periph/s01_couplers/auto_pc/S_AXI(zed_hdmi_processing_system7_0_0_FCLK_CLK0) and /axi_vdma_0/M_AXI_MM2S(zed_hdmi_processing_system7_0_0_FCLK_CLK1)

CRITICAL WARNING: [BD 41-237] Bus Interface property TDATA_NUM_BYTES does not match between /fmc_imageon_hdmio_rgb/v_rgb2ycrcb_0/video_in(3) and /axi_vdma_0/M_AXIS_MM2S(4)

ERROR: [BD 41-237] Bus Interface property FREQ_HZ does not match between /axi_vdma_0/S_AXIS_S2MM(100000000) and /fmc_imageon_vita_color/v_cfa_0/video_out(142857132)

ERROR: [BD 41-237] Bus Interface property CLK_DOMAIN does not match between /axi_vdma_0/S_AXIS_S2MM(zed_hdmi_processing_system7_0_0_FCLK_CLK0) and /fmc_imageon_vita_color/v_cfa_0/video_out(zed_hdmi_processing_system7_0_0_FCLK_CLK1)

Are there any good examples that will show me how to connect up the VDMA?

0 albertabeef over 11 years ago

Take a look at the HDMI Display Controller tutorial, which illustrates how to add a VDMA core.
The tutorial only enables the VDMA core for the video output path, but will serve as an example.
It illustrates how to address the TDATA_NUM_BYTES issue by adding a "AXI4-Stream Subset Converter" core.
Regards,
Mario.
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel
0 Former Member over 11 years ago

I have already done that. In this design the VDMA doesn't have a video input. I'm want to know how to configure the VDMA when using the video input.
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel
0 Former Member over 11 years ago

Hi,

The errors you are getting should be quite easy to fix, it seems that you have simply swapped the clock connections on the VDMA between the MM2S and S2MM connections and therefore the clock domains are wrong.

The critical warning is telling you that the VDMA is sending 4 bytes of data but the rgb2ycrcb module is only reading 3, you can use an AXIS data width converter to sort this out.

For examples I would suggest Xapp794, it applies to the ZC702 but you should be able to use the same hardware architecture.

http://www.xilinx.com/support/documentation/application_notes/xapp794-1080p60-camera.pdf

Matthew
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel