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Shared data cache between PS and custom IP

Former Member

Hello, I would like to use a share data cache (L2) between the PS and one custom IP.

I used the System Cache IP, connected to M_GP0.
The L2 cache should be placed before the DDR memory.

The architecture of the system is available here : http://img15.hostingpics.net/pics/171358architecture.png

The memory mapping is available here :
http://img15.hostingpics.net/pics/611571memorymapping.png

After looking with the ILA, no data is present on the while debugging with SDK

  • 0

    I could not understand your architecture's picture: the PS is directly connected to an external DDR, and you say that it should be placed after the "System Cache IP"...

    Maybe you think on a Microblaze, instead of the PS, connected to the system_cache_0 through the axi_interconnect_0.

    In addition, you say that no data is present in the ILA while debugging with SDK. Is the complete system working without the ILA?

    I would suggest to try first a simple memory, instead of a custom IP.

  • 0

    Hello, thank you for your answer.
    Sorry for not being clear, I will try to explain it again....

    "I could not understand your architecture's picture: the PS is directly connected to an external DDR, and you say that it should be placed after the "System Cache IP"..."

    My idea was to access the DDR through a slave port of the PS (I discovered that the HP ports were more suitable for this so I use one of them instead).

    I finally succeed to acces the DDR memory from the M_AXI_GP0 port by making an adresss translation from PL region to DDR region with a custom module place inside the path (cf http://img15.hostingpics.net/pics/542935PLtoDDR.png).
    I choose this option because it was not possible to access directly the DDR from the address editor.

    "In addition, you say that no data is present in the ILA while debugging with SDK. Is the complete system working without the ILA?"

    Here I meant data coming from the M_GP0 port and going through System Cache, this problem was solved by  adding the addressTranslation module and modifying the linker script inside SDK. With the test architecture posted in this post, the memory address observed with the ILA correspond to the DDR region (0010_0000 to 3FFF_FFFF).

    Right now I'm a bit confused concerning the timings I got while executing my program (RSA decryption implemented with mini-gmp library)...

    The decryption is actually faster if I compare the architecture mentionned in this post with the same one without System Cache (around 9 seconds vs 2.65 seconds).
    Moreover, the decryption is also  faster (0.02 seconds vs 2.65 seconds) if the program is directly mapped in the DDR (with the linker script inside SDK) instead of accessing the DDR via the PL path.

  • 0

    Hi there,

    I'm a bit confused as to why you are accessing the L2 cache instead of the DDR?  Is there a specific reason for this?  Using built in Zynq features you can readily access the DDR memory from either the PS or PL so it ends up a great place to allow the SNOOP controller to manage accesses / etc. making life a lot easier for you.

    --Dan