Errata: USB Host cap slightly out-of-spec

Please be aware that we are slightly out-of-spec on a capacitor that is required to put the TUSB1210 USB PHY into Host mode. C89 correctly shows as 120uF in the schematic. However, 100uF is populated. I don’t expect this to be a problem, but it is a possibility. Those concerned with meeting this specification should change out C89 for 120uF. Here is an explanation from TI Engineering regarding the possible implications:

USB2.0 OTG2.0 spec max ext cap on VBUS is 6.5uF on Host side and 6.5uF on Device side (13uF total). Host only application requires > 120uF (CHPB in USB2.0 Table7-7).

OTG2.0 ADP (and OTG1.3 VBUS pulsing) make use of the differences in VBUS capacitances for detections.

So you must provide the VBUS capacitance according to the target specification.

I will be publishing an errata to this effect shortly.

Bryan

0 Former Member over 13 years ago

Should we collect all Zedboard effected errata in same place
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0 bhfletcher over 13 years ago

Yes, I am working on a document that will be posted in the Documentation area. I'm trying to figure out from our CM how to identify this first batch of boards vs. the next batch which will be populated correctly. The PCB will still be Revision C.

Are you aware of other Board-related errata? I do not plan on keeping track of ES silicon errata or tools errata which are already being done by Xilinx.

Thanks,
Bryan
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0 bhfletcher over 13 years ago
I thought of 3 more that I will also add to the document.

Since the ZedBoard uses ES silicon, the Zynq errata affects ZedBoard. Everyone should read and understand the errata affecting the 7Z020.

DDR3 CKE is now recommended to be pulled up through 40-ohms to VTT. We have not seen any failures related to this.

SD_CLK is now recommended to be terminated with a 40 to 60-ohm series resistor. We have not seen any failures related to this.
Bryan
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