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Dating rising edges

Former Member

Hello everyone,

I'm working with a ZedBoard REV D and VIVADO 2014.3 and I'm quite new to FPGA programming.

I'm trying to date a few (~10) successive rising edge of a periodic logic signal (square 0-2.5V) at around 10MHz. Basically I'm building a frequency meter.

What i did so far in VIVADO:
-I created a 16 bit-wide binary counter driven by a 100MHz clock (precision isn't a matter, for now) and retrieve its value in the PS via an AXI GPIO block.
-I used the XADC-GIO0 pin (H15) to acquire my logic signal via an AXI GPIO block.

And here i simply export my bitstream to SDK and using the Xil_In32 function i wait for a rising edge and get the counter value when it occurs. It works well at low frequency (<1MHz) but not above.

I obviously need to retrieve my counter value in the PL domain to reach the desired frequency (10MHz). And here I'm lost because i don't know how to do that. I've checked forums for the last few days and get even more lost.. I tried many things without success.

I simply need to transfer my counter value to a memory register when a rising edge of my signal occurs and retrieve these values afterward in the PS (there can be timeouts between measurements) but i don't know how. Using interrupts? RAM shift registers?

Any hint/advice/suggestion is very welcome.

Thanks a lot for reading me.

Alexis

  • 0

    I hope I am reading and understanding your question, so if I make a mistake please post back so we can get you up and running!

    First, what resets your counter?  Is it a single latch, or does it start the count over each time the "10MHz" clock comes in?

    What I am thinking, since you KNOW you want to get 10 values, you can take the counter and have the counter's value fed into a FIFO.  When you would normally get your TRIGGER to read the counter, use that signal to enable the FIFO for 1 clock.  This will retain the values for you.

    From there, you can read the FIFO using an AXI block, almost as you have mentioned you have done.  If you want to to get fancy, you can setup the FIFO to have a watermark, so when you get 10 samples, it can cause an interrupt, which you would then service by reading (emptying) the fifo.

    Be mindful of crossing clock domains! 

    --Dan

  • 0

    Hello zedman2000, sorry for the late reply and thanks for your answer.
    Actually my counter is free running but something else is annoying me.
    The trigger which tell the moment to retrieve my counter value might be an interrupt generated by the GPIO that acquire my 10MHz, right?
    But in order to setup my interrupt (in the SDK) i need to know my GPIO DEVICE ID, which i can't find anywhere (i checked many header files, including xparameters.h). I only know its base address (assigned in vivado).
    Thanks for reading.
    Alexis

  • 0 in reply to Former Member

    Well i found something interesting !
    When i modify my block diagram in vivado (like adding an AXI GPIO block) the file parameters.h (in SDK) isn't updated with a new GPIO instance. I have to create a new project to find it in my new parameters.h file.
    I'm improving since i start quite from the bottom :)

    PS:i could edit my previous message so i created a new one.