Hello everyone,
I'm working with a ZedBoard REV D and VIVADO 2014.3 and I'm quite new to FPGA programming.
I'm trying to date a few (~10) successive rising edge of a periodic logic signal (square 0-2.5V) at around 10MHz. Basically I'm building a frequency meter.
What i did so far in VIVADO:
-I created a 16 bit-wide binary counter driven by a 100MHz clock (precision isn't a matter, for now) and retrieve its value in the PS via an AXI GPIO block.
-I used the XADC-GIO0 pin (H15) to acquire my logic signal via an AXI GPIO block.
And here i simply export my bitstream to SDK and using the Xil_In32 function i wait for a rising edge and get the counter value when it occurs. It works well at low frequency (<1MHz) but not above.
I obviously need to retrieve my counter value in the PL domain to reach the desired frequency (10MHz). And here I'm lost because i don't know how to do that. I've checked forums for the last few days and get even more lost.. I tried many things without success.
I simply need to transfer my counter value to a memory register when a rising edge of my signal occurs and retrieve these values afterward in the PS (there can be timeouts between measurements) but i don't know how. Using interrupts? RAM shift registers?
Any hint/advice/suggestion is very welcome.
Thanks a lot for reading me.
Alexis
