Understanding Ethernet on Zedboard

Question

Hi Everyone!

I am not very experienced with the Zedboard and having a ruff time understanding the infrastructure around the Ethernet functionality on the Zedboard.

I have read the related chapters in the following documents, but so far I was not able to put it all together.

1 Zedboard HW User Guide Version 1.1
2 UG585 (v1.10) February 23, 2015
3 various posts such as:
http://zedboard.org/content/redirecting-peripherals-mio-emio

So, as far as I understand there is a Marvell Ethernet PHY on the Zedboard which is directly connected to the PS's MIO Bank 1(via RGMII). Further more, there are two Ethernet MACs in the Processing System which are also connected to the MIO Bank via RGMII(over a GMII/RGMII adapter). Additionally, these two Ethernet MACs are connected to the Zedboards DDR3 RAM via a DMA Controller.

Question A:
Is that correct? Did I miss something important?

One of my goals is to get Ethernet frames/packets into the PL where I want to build some logic to analyse Headers etc.. (proof of concept / educational work)

Similar to Link 3 I redirected eth0 to EMIO(I am working with Vivado btw) and got a MDIO and a GMII Port added to my Processing System block view.

Question B:
Where exactly are these interfaces(GMII and MDIO) connected to? I think to one of the Ethernet MACs of the PS?!

Question(s) C:
What do I have to do now in order to get Ethernet packets to my custom IP?
Do I have to initialize the Ethernet MAC of the PS using DMA(from one of the arm cores) like described in 2 and get packets from RAM to my IP?
Or is there a way to get packets over the above mentioned GMII?
Or is it possible to get a direct connection to the Marvell PHY?

kind regards and a big thank you in advance!

PS:Sorry for the bad formatting.. I added blank lines but paragraphs are not recognized appropriately

Former Member · Accepted Answer

Take a look at the Avnet Zynq SW and HW Speedway workshop material, it will give you a detailed description of the Zynq internals. There are also hands on labs that target the ZedBoard. Developing Zynq -7000 All Programmable SoC Software (Vivado 2013.3 and 2014.4.1) Developing Zynq -7000 All Programmable SoC Hardware (Vivado 2013.3 and 2014.4.1) That said, here is a quick sketch of how the Zedboard utilizes the Zynq Ethernet. There are two Ethernet MACs in the PS (Processing System) portion of the Zynq device. The first of these, ETH0 is connected, via the Zynq MIO interface, directly to a Marvell Ethernet PHY on the ZedBoard using an RGMII interface. This Ethernet interface is 'free' on the Zedboard and is what most applications and Operating Systems use to connect. The second Ethernet MAC in the Zynq PS, ETH1, cannot be connected directly via the MIO pins due to their multiplexed nature and the other peripherals on the ZedBoard connected to them. To use the second Ethernet MAC you would need to route it's interface signals through the PL (Programmable Logic) portion of the Zynq device. Then you would need to connect these signals (as a GMII interface) to external Zynq pins connected to a PHY that you would have to provide on one of the external ZedBoard connectors such as the FMC connector. It is also possible to use a PHY with an RGMII interface by using a GMII to RGMII 'shim' IP within the Zynq PL. Unless you need a second Ethernet port, or have a specific interface requirement that the Marvell PHY on the ZedBoard does not support, you will not need to use the second Ethernet MAC. You can program the Ethernet MAC and DMA controller to transfer the data to any memory area available. Typically this is in the ZedBoard DDR memory but it could be a custom memory area that you have defined and created in the Zynq PL section. Most likely you will want to just move the data from the DDR to your custom IP. If you are going to implement this in a 'bare metal' fashion you may want to take a look at the code include with the LWiP example provided in the SDK. If you plan to use Linux or some other OS you will need to investigate how to move the data within the OS framework. -Gary