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How to change defaults values of hardware registers?

Former Member

Hi.
I would like to change default FCLK and Ethernet clock source.
I need to set FCLK to 125 MHz and Ethernet clock source to EMIO.

What is the right way to do it? How can I check my new setting after Zedboard boots up?

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  • 0

    In Vivado open your block design and then double click on the Zynq Processing System to change the settings. Open up the 'Clock Configuration', select FCLK you want, and then set the Requested Frequency to 125.  I don't believe that you can change the clock source of one of the internal Ethernet MACs in the Zynq Processing System (PS) section to EMIO independently of the other Ethernet interface signals. You can select the Ethernet MAC interface signals to be either all MIO or all EMIO. To change the signal interface to EMIO, while still in the Zynq Processing System Dialog, select the 'MIO Configuration' option in the Page Navigator, select and enable the ENET you want to use and then change the IO selection from MIO to EMIO.

     

    When you are done you will need to validate and save your block design and re-run the synthesis and implementation steps.

     

    -Gary

  • 0 in reply to Former Member

    Hi Gray,
    thanks for help.
    I think you misunderstood me. I'm interested in the way of how to change System Level Control Registers of Zynq.
    GEM0_RCLK_CTRL uFFFC0x00000138
    GEM0_CLK_CTRL uFFFC0x00000140
    According to Technical Reference Manual some bits of these registers define clock source for Ethernet controller.

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