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How to change defaults values of hardware registers?

Former Member

Hi.
I would like to change default FCLK and Ethernet clock source.
I need to set FCLK to 125 MHz and Ethernet clock source to EMIO.

What is the right way to do it? How can I check my new setting after Zedboard boots up?

  • 0

    In Vivado open your block design and then double click on the Zynq Processing System to change the settings. Open up the 'Clock Configuration', select FCLK you want, and then set the Requested Frequency to 125.  I don't believe that you can change the clock source of one of the internal Ethernet MACs in the Zynq Processing System (PS) section to EMIO independently of the other Ethernet interface signals. You can select the Ethernet MAC interface signals to be either all MIO or all EMIO. To change the signal interface to EMIO, while still in the Zynq Processing System Dialog, select the 'MIO Configuration' option in the Page Navigator, select and enable the ENET you want to use and then change the IO selection from MIO to EMIO.

     

    When you are done you will need to validate and save your block design and re-run the synthesis and implementation steps.

     

    -Gary

  • 0 in reply to Former Member

    Hi Gray,
    thanks for help.
    I think you misunderstood me. I'm interested in the way of how to change System Level Control Registers of Zynq.
    GEM0_RCLK_CTRL uFFFC0x00000138
    GEM0_CLK_CTRL uFFFC0x00000140
    According to Technical Reference Manual some bits of these registers define clock source for Ethernet controller.

  • 0

    Look at the ps7_init.c that you exported from Vivado/ISE to your SDK project and you can see how the SLCR registers are being programmed. Ps7_init.html is the same information in a graphical format. You can program the register in the same manner as the ps7_init.c code does, but you should have a very good understanding of how all of the Ethernet and clock  control registers interact with each other before attempting this.

     

    I am not sure what you are trying to accomplish by directly writing these registers. If you have set the Ethernet MAC to use EMIO interfacing then all you need to do is connect the output of your clock source (Your FCLK I guess?) to the MII/GMII interface signals as described in the Technical Reference Manual (see section 25.6.2). If you want to use the PS based FCLK just configure it as described above. Alternatively you can use the resources in the Programmable Logic (PL) section of the Zynq to generate a clock source or provide one from an external pin.

     

    If you are trying to configure the Ethernet MAC in the Zynq Processing Subsystem (PS) to use the external RGMII PHY but substitute an internal clock source via the EMIO I am not sure how that would work.

     

    -Gary

  • 0

    Gary,
    here is description of what I'm trying to do.
    1. I have Zedboard.
    2. I have my own IP core which uses GMII interface to send/receive data. Standard IP/UDP packets are used.
    3. I'd like to redirect signals of Eth controller to PL so make a connection between PS and PL via GMII.

    I tried to just redirect signals according to this note http://zedboard.org/content/redirecting-peripherals-mio-emio

    But I doesn't help. I see packets from PS (linux) but PS (linux) doesn't see packets from my core.
    I suppose the problem is that Eth controller is still using clocks from PHY. So I'm trying to tell Eth controller to use clocks from EMIO.

    I would very appreciate if you help me with this problem.

  • 0

    If you follow the steps outlined in the note you refer to and then connect your clock sources to the 'exposed' GMII signals the Ethernet controller will be using your clocks and not the clocks from the PHY.

     

    image

     

    -Gary

  • 0

    The note just explain how to redirect signals.
    According to the figure 25-7, section 25.6.2 of the Technical Reference Manual Tx and Rx clocks have 2 possible inputs each (from MIO anf EMIO) trough programmable multiplexer.
    As I understand Ethernet controller by default gets clocks from MIO and switch it to EMIO registers GEM0_RCLK_CTRL and GEM0_CLK_CTRL should be written with new values (Appendix B: Register Details).

  • 0

    If you follow the steps in the note you referred to, the tools will take care of setting up the GEM0 register values for you in the generated ps7_init.c/ps7_init.tcl files. Unless you need to dynamically change the Ethernet clock source after Zynq device has booted there is no need to directly write these registers.

     

    -Gary

  • 0

    Hello! I have simillar problem with connection PS to PL via GMII(EMIO)

    PS part don't receives data from PL. But frames from PS pass via PL to PHY and I can see them with WireShark. I checked RX part with ChipScope and I do observe correct data on PS RX inputs. I checked MAC and SLCR registers, and I judge they are fine.

    I connected dead simple loopback - wired TX to RX, TX_CLK and RX_CLK are sourced with 125 MHz, Link is 1Gbit. No packet received.

    But when I just set loopback bit in GEM.net_ctrl register - I managed to ping self from U-boot, so I come with idea that it's matter of connection PL to PS. For now I've tryed bitstream made in Vivado 2014.2 and 2014.1, GEM0 and GEM1 and no luck.

    Any Ideas? Do you resolved your problem?

    - Thanks for attention.
    - Nikolay