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How to change defaults values of hardware registers?

Former Member

Hi.
I would like to change default FCLK and Ethernet clock source.
I need to set FCLK to 125 MHz and Ethernet clock source to EMIO.

What is the right way to do it? How can I check my new setting after Zedboard boots up?

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    Look at the ps7_init.c that you exported from Vivado/ISE to your SDK project and you can see how the SLCR registers are being programmed. Ps7_init.html is the same information in a graphical format. You can program the register in the same manner as the ps7_init.c code does, but you should have a very good understanding of how all of the Ethernet and clock  control registers interact with each other before attempting this.

     

    I am not sure what you are trying to accomplish by directly writing these registers. If you have set the Ethernet MAC to use EMIO interfacing then all you need to do is connect the output of your clock source (Your FCLK I guess?) to the MII/GMII interface signals as described in the Technical Reference Manual (see section 25.6.2). If you want to use the PS based FCLK just configure it as described above. Alternatively you can use the resources in the Programmable Logic (PL) section of the Zynq to generate a clock source or provide one from an external pin.

     

    If you are trying to configure the Ethernet MAC in the Zynq Processing Subsystem (PS) to use the external RGMII PHY but substitute an internal clock source via the EMIO I am not sure how that would work.

     

    -Gary

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  • 0

    Look at the ps7_init.c that you exported from Vivado/ISE to your SDK project and you can see how the SLCR registers are being programmed. Ps7_init.html is the same information in a graphical format. You can program the register in the same manner as the ps7_init.c code does, but you should have a very good understanding of how all of the Ethernet and clock  control registers interact with each other before attempting this.

     

    I am not sure what you are trying to accomplish by directly writing these registers. If you have set the Ethernet MAC to use EMIO interfacing then all you need to do is connect the output of your clock source (Your FCLK I guess?) to the MII/GMII interface signals as described in the Technical Reference Manual (see section 25.6.2). If you want to use the PS based FCLK just configure it as described above. Alternatively you can use the resources in the Programmable Logic (PL) section of the Zynq to generate a clock source or provide one from an external pin.

     

    If you are trying to configure the Ethernet MAC in the Zynq Processing Subsystem (PS) to use the external RGMII PHY but substitute an internal clock source via the EMIO I am not sure how that would work.

     

    -Gary

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