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How to change defaults values of hardware registers?

Former Member

Hi.
I would like to change default FCLK and Ethernet clock source.
I need to set FCLK to 125 MHz and Ethernet clock source to EMIO.

What is the right way to do it? How can I check my new setting after Zedboard boots up?

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    Hello! I have simillar problem with connection PS to PL via GMII(EMIO)

    PS part don't receives data from PL. But frames from PS pass via PL to PHY and I can see them with WireShark. I checked RX part with ChipScope and I do observe correct data on PS RX inputs. I checked MAC and SLCR registers, and I judge they are fine.

    I connected dead simple loopback - wired TX to RX, TX_CLK and RX_CLK are sourced with 125 MHz, Link is 1Gbit. No packet received.

    But when I just set loopback bit in GEM.net_ctrl register - I managed to ping self from U-boot, so I come with idea that it's matter of connection PL to PS. For now I've tryed bitstream made in Vivado 2014.2 and 2014.1, GEM0 and GEM1 and no luck.

    Any Ideas? Do you resolved your problem?

    - Thanks for attention.
    - Nikolay

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  • 0

    Hello! I have simillar problem with connection PS to PL via GMII(EMIO)

    PS part don't receives data from PL. But frames from PS pass via PL to PHY and I can see them with WireShark. I checked RX part with ChipScope and I do observe correct data on PS RX inputs. I checked MAC and SLCR registers, and I judge they are fine.

    I connected dead simple loopback - wired TX to RX, TX_CLK and RX_CLK are sourced with 125 MHz, Link is 1Gbit. No packet received.

    But when I just set loopback bit in GEM.net_ctrl register - I managed to ping self from U-boot, so I come with idea that it's matter of connection PL to PS. For now I've tryed bitstream made in Vivado 2014.2 and 2014.1, GEM0 and GEM1 and no luck.

    Any Ideas? Do you resolved your problem?

    - Thanks for attention.
    - Nikolay

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