design failed to meet timing constraints

Hello Every one,In my design i am using to clock one is at 100MHz and another one is at 200MHz.After synthesis when i implementing the design i got an error as design failed to meet timing constraints,Hence anyone please help me how to resolve this issue.

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0 jafoste4 over 8 years ago

Hi babuji,
Seeing how you are using a xilinx board I am going to suggest you ask your question over there as they are they are more familiar with your hardware.
https://forums.xilinx.com/
However, you should first check your timing report to get an idea what failed.
--Josh
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0 jafoste4 over 8 years ago

Hi babuji,
Seeing how you are using a xilinx board I am going to suggest you ask your question over there as they are they are more familiar with your hardware.
https://forums.xilinx.com/
However, you should first check your timing report to get an idea what failed.
--Josh
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