I have a design with multiple buffers (128 element-long arrays storing 32 bit numbers) and during the synthesis I have came across following warning in the Synthesis Log:
ROM "read_buffer_reg[0]" won't be mapped to RAM because address size (32) is larger than maximum supported(18)
ROM "read_buffer_reg[1]" won't be mapped to RAM because address size (32) is larger than maximum supported(18)
... all the way to 127
I have somehow assumed, that the reason, why it cannot be mapped to RAM is that element size is 32 bits, so I have broken down the buffer into 2 smaller buffers,128 element-long buffers with 16 bit value per element. But the problem persists:
ROM "read_buffer_1_reg[0]" won't be mapped to RAM because address size (32) is larger than maximum supported(18)
ROM "read_buffer_1_reg[1]" won't be mapped to RAM because address size (32) is larger than maximum supported(18)
... all the way to 127
The trick seems to be in the "address size", but my buffers are long only 128 elements, that should be easily addressable by 1 byte (only 7 bits actually).
So is there a way to make the Synthesis Tool utilize the RAMB instead of other logic when it comes to such buffers?
P.S.
I have tried the following
ttype mem_buffer_short is array (0 to 127) of std_logic_vector(15 downto 0);
tsignal read_buffer_0 : mem_buffer_short;
tsignal read_buffer_1 : mem_buffer_short;
tattribute ram_style: string;
tattribute ram_style of read_buffer_0: signal is "block";
tattribute ram_style of read_buffer_1: signal is "block";
but I got the following message
WARNING: [Synth 8-3514] cannot infer block ram on a non-memory variable 'read_buffer_0' [c:/xilinx_projects_2014/fft_generator_test_01/ip_vga_axi_driver_3.6/src/VGA_stream.vhd:219]
INFO: [Synth 8-4472] Detected and applied attribute ram_style = block [c:/xilinx_projects_2014/fft_generator_test_01/ip_vga_axi_driver_3.6/src/VGA_stream.vhd:216]
WARNING: [Synth 8-3514] cannot infer block ram on a non-memory variable 'read_buffer_1' [c:/xilinx_projects_2014/fft_generator_test_01/ip_vga_axi_driver_3.6/src/VGA_stream.vhd:220]
INFO: [Synth 8-4472] Detected and applied attribute ram_style = block [c:/xilinx_projects_2014/fft_generator_test_01/ip_vga_axi_driver_3.6/src/VGA_stream.vhd:217]
