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UART0 routed to PL via EMIO does not send any data out

fayyazrafiq

Hi,

I am having the EMIO problem. I wanted to use PS UART0 via EMIO and connected it to PL side package pins in XPS, but i could see any data out after several tries.  I am using XPS 14.5 and SDK 14.5 with ZEDBOARD.

I also tried the XMD debugger and I can see the UART0 data out via PL package pins. I don't know where is the problem but i am struggling this problem from one week. please help me.

Any help is highly appreciated.

Regards
Fayyaz

  • 0

    Hello Fayyaz,

     

    I do not have 14.5 loaded but I do have 14.7, so I built up a new design using PlanAhead, in a similar fashion to the Concepts, Tools and Techniques tutorial for 14.5 located here: http://www.zedboard.org/design/1521/11

     

    In addition to the base design from the tutorial I added UART 0 with EMIO connections. I made the UART0 TX and RX ports 'External' and exited XPS. I then created a Top HDL file and used the signal names assigned there to add constraints to connect the UART 0 TX and RX signals to one of the ZedBoard PMOD connectors in a constraints file I created. I implemented the design and generated a bitstream and then 'exported' the design to SDK. There I generated a basic 'Hello World' application. Note that when you enable UART0 it will become the sdin/sdout port for the SDK applications. I connected a terminal to an RS232 converter connected to the Zedboard PMOD with the UART0 TX and RX signals, loaded the FPGA bitstream, and then ran the 'Hello World' application. I get the "Hello World" output on the terminal connected to UART0 via the RS232 converter on the PMOD connection.

     

    I have done a similar design with Vivado 2031.4 and it works as well.

     

    You might want to complete a like design to verify your tools and hardware operation. Please make sure you have made the UART0 ports External, added a constraints file, loaded the FPGA bitstream, and remember that the PMOD signals are LVCMOS33 signal levels. If you are still having issues one thing I have seen cause odd issues is a corrupt Xilinx tools installation. If you still have the archive file you downloaded to install your Xilinx tools you might want to verify that the MD5 sum is correct and matches the one published on the Xilinx download site.

     

    -Gary

  • 0

    Hi Gary,

    I duplicated your instructions using Vivado 2017.2 but was not able to read anything off the TX and RX lines in my Picozed 7030 via CC V2. Here's what I did (and hopefully you might be able to see what I did wrong?):

    1. UART0 --> EMIO

    2. UART0 TX [external] --> to pin AA17 (Picozed)/JB PMOD, Pin 1 --> constraints file.

    3. UART0 RX [external] --> to pin AA16 (Picozed)JB PMOD, Pin 2 --> constrainst file.

    ie...

    set_property PACKAGE_PIN AA16 [get_ports UART0_RX]

    set_property PACKAGE_PIN AA17 [get_ports UART0_TX]

    4. Synthesized/Implemented and Generated Bitstream with no issues

    5. Export Hardware (including Bitstream) and opened the SDK

    6. In Board Support Package Settings: stdin and stdout is set to ps7_uart_0

    7. Generated Hello World using:

    a) File --> New --> Application Project --> Hello World example project...

    b) In system.mss, under peripheral drivers --> ps7_uart_0 --> Import examples --> Hello World example project...

     

    I ran both methods for step 7 but with no success. Nothing popped up on my terminal.

    Serial settings:

    Baud: 115200 (set in Vivado hardware and matched to terminal program)

    TX (Picozed) <---> RX (terminal)

    RX (Picozed) <--> TX (terminal)

    GND <--> GND

     

    Did I miss anything?


    Thank you.
     

    Regards,


    Ron.

  • 0 in reply to rwong1231

    One more thing: after regenerating the BSP sources, the problem window displayed the following message:

    missing initializer for field 'HandlerTable' of 'XScuGic_Config {aka struct <anonymous>}' [-Wmissing-field-initializers]

    I'm not sure if this may contribute to the issue I'm having but am putting it in here in case it does.

    Severity: warning

    Ron.

  • 0 in reply to rwong1231

    Bank 13

    IO Std: LVCMOS33

    Drive strength: (nothing for RX) but TX is set to 12

    Slew: slow

    Pull-type: None

    Off-chip termination: None