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ZedBoard Hardware Design FIR Compiler 7.1 in Vivado 2013.2
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FIR Compiler 7.1 in Vivado 2013.2

Former Member
Former Member over 12 years ago

Hi

I was wondering if anyone has managed to use the FIR Compiler IP in Vivado 2013.2. The overall aim of my project is to perform audio filtering of data connected from the audio codec. At the moment though, I am just focusing on trying to get anything to come out of the other side of the filter!

I have found no examples online of how to use it, and do not find the information in the product guide very helpful!

My understanding is that to send data from the PS to the filter, and then get it back again, you would place the following blocks:
http://personal.strath.ac.uk/kenneth.barlee/zed_posts/fir_connection.png

First off - is this correct?!

Deleting the FIR block and just connecting the AXI_STR_TXD and AXI_STR_RXD ports on the AXI_Stream FIFO together, I am able to send and then receive data. When I stick the FIR in though, nothing comes out of it. If it is connected correctly, then presumably something is wrong in the settings of the IP block.

Has anyone done anything like this before who would like to share ...?!

Thanks

Kenny

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  • Former Member
    0 Former Member over 11 years ago

    Hi..
    finally i have completed a model for fir filtering uaing the fir compiler. Instead of using the fifo i have used dma. the model works fine.

    The following is the link to the solution
    http://forums.xilinx.com/t5/Embedded-Processor-System-Design/FIR-compiler-and-PS/m-p/547409#M13571

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  • Former Member
    0 Former Member over 11 years ago

    Hi..
    finally i have completed a model for fir filtering uaing the fir compiler. Instead of using the fifo i have used dma. the model works fine.

    The following is the link to the solution
    http://forums.xilinx.com/t5/Embedded-Processor-System-Design/FIR-compiler-and-PS/m-p/547409#M13571

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