Configure PL Clocks When Using Linux

Hello,

How do I configure FCLK0 when using the Zedboard with Linux?

I have designed and tested on bare metal a peripheral I have created. For its use I have configured FCLK0 to be 10MHz. The clock configuration works and has been verified on the oscilloscope.

I have created an FSBL from the same hardware, and used that to create a boot.bin. I've replaced the default boot.bin with my new one on the SD card.

While the system boots I see the blue light go on, then on the oscope I can see the FCLK0 (I have it routed to a pin on a pMod) stabilize at 10MHz. Seems great, but a few seconds later the clock reconfigures to 100MHz (stock).

Any insight to why this is happening, and what I can do to fix it would be greatly appreciated.

Sincereley, Phil

0 bhfletcher over 12 years ago

When you say, "I have configured FCLK0 to be 10MHz," how are you doing that? There are ways to do this in software, but you really should go back to the hardware platform in XPS, change it there, and then regenerate the hardware platform and BSP.
Bryan
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel
0 Former Member over 12 years ago in reply to bhfletcher

Thank you for expressing interest in helping me. I've got my system working with a bit of a hack- instead of reconfiguring FCLK0, I leave it at 100MHz and added in a 'clock wizard' to the system to bump it down to 10Mhz- my project is working now. I'd still like to know if you have any ideas off the top of your head, so I will explain in more detail what I am experiencing.

I configured it in the hardware, regenerated hardware platform and BSP. At that point the 10MHz is correctly and verifiably set when using the bare metal. When use that hardware to generate an FSBL and make a boot.bin out of the new FSBL, bitfile, and a copy of u-boot the system configures for 10MHz (seen on scope) but it only sticks for about 10 seconds, at which point some part of the system sets it back to 100MHz.
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel
0 bhfletcher over 12 years ago in reply to Former Member

Sounds like the FSBL is hard-coded for 100 MHz. What version of Xilinx tools are you using?
Bryan
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel
0 Former Member over 12 years ago in reply to bhfletcher

I'm using 14.4. I just find it strange that I see the 10MHz momentarily. Thanks for the suggestions, my system is working now so I guess I'll just go with that and enjoy that it is no longer broken.
-Phil
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel