I am using Xillinux and editing the file xillydemo. I have tried to insert a new clock by generating IP by using the clocking wizard in the xilinx core generator. I generate the core, then I take the UCF file and merge it with the xillinux one and I add the verilog file to my xillinux (xillydemo) project and parameterize it as a module by passing in clk_100 (GCLK under Y9) under CLK_IN1 and taking out CLK_OUT1. It keeps giving me an error saying that "Port <clk_100> has illegal connections. This port is connected to an input buffer and other components." even if I don't directly patch clk_100 in but instead assign it to another wire and feed that into the module. I know how to remove this warning under the sythesis properties but that doesn't seem like the right thing to do. I would rather figure out why it is giving an error and fix it (removing the error forcefully only generates more errors). Thanks!!
