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ZYNQ 7020 BANK 33 differential

e14 Contributor

Hi guys,
iu00B4ve some problems with the zynq 7020 board. I try to connect a differential signal from the Artix7 FPGA to the PMOD Connector JC1.
It is possible to drive each pin with an single ended signal, but with an differential signal the pins have an level of 190 mV with a jitter in the freqency of the signal.
The differential signal is driven by an OBUFDS instance with the io-standard LVDS_25.
In the ucf-file the pins are declared as LVDS_25 too.
Do you have any idea to solve this problem?
Whats wrong in the design?
Thanks

  • 0

    The supply voltage of the Bank33 is 3.3V. Which IO-standard is possible?

  • 0

    Hi Gerhard,

    Which way is your signal going? Are you transmitting from ZedBoard to the Artix-7 FPGA board?

    If so, I am surprised you are seeing any signals there at all. Those traces are routed differentially, however they connect to a 3.3V powered I/O bank on the Z7020 device with which I do not believe it is valid to drive LVDS_25 to/from these I/O pins due to the bank voltage.

    One way that we have worked around this to drive out to an LVDS display is to add the following to our Pmod design:

    Hardware
    u2022 Add 49R9 1% pull up on all differential signals (D0_P/N ~ D3P/N and CLK_P/N)
    u2022 Add LDO using 3.3V input to generate 1.5V output and connected to those pull up resistors

    FPGA design
    u2022 Only change required is the selection of IO standard TMDS_33 on the related signals

    Hopefully something similar might help you in your application.

    Regards,

    -Kevin

  • 0 in reply to zedhed

    Hi,

    the signal is a output of the Zynq chip on the z-Board. Itu00B4s a clock signal for an image sensor connected to the pmod JC1 connector.
    My solution of this problem is in the moment: Take the signal and the inverted signal from the MMCM modul and connect each to one ODDR. It works, but it is not exactly differential. Iu00B4ll try the TMDS_33 standard out tomorrow (german time:)).

    Gerhard