Hi guys,
iu00B4ve some problems with the zynq 7020 board. I try to connect a differential signal from the Artix7 FPGA to the PMOD Connector JC1.
It is possible to drive each pin with an single ended signal, but with an differential signal the pins have an level of 190 mV with a jitter in the freqency of the signal.
The differential signal is driven by an OBUFDS instance with the io-standard LVDS_25.
In the ucf-file the pins are declared as LVDS_25 too.
Do you have any idea to solve this problem?
Whats wrong in the design?
Thanks
