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Run-Time Reconfiguration on ZedBoard

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Hi everybody,
I'm working with a ZedBoard and my goal is to set up a run-time reconfigurable platform. I need a processor with some reconfigurable accelerator on its side.
I'm new to this platform and Xilinx tools, so I'm asking your help about important points:

-it's easier to use the included ARM dual-core processor or to use a MicroBlaze soft-processor to set-up a reconfigurable architecture?

-I found lots of guides and documentation by Xilinx and ZedBoard, but what is the workflow you suggest me to start working on this new platform?

-do you know any step by step tutorial to start working using the tipical Xilinx workflow on a ZedBoard?

Thanks in advanace!

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    I followed a tutorial to create an HW accelerator for the PL in order to work together with the ARM PS.
    I used the following work-flow:

    ->VIVADO HLS:
    -->c simulation
    -->c synthesis
    -->c/rtl co-simulation
    -->export ip

    ->VIVADO DESIGN SUITE
    -->create block design
    -->generate output file
    -->generate hdl wrapper
    -->generate bitstream
    -->export hardware
    -->launch sdk

    ->XILINX SDK
    -->create bsp
    -->create application

    Now I have some questions:

    - If I want to use the PCAP interface to partially reconfigure the PL run-time how have I to modify the work-flow?

    - Have I to add some specific block in the block design to be able to use the PCAP?

    Thanks in advance

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  • 0

    I followed a tutorial to create an HW accelerator for the PL in order to work together with the ARM PS.
    I used the following work-flow:

    ->VIVADO HLS:
    -->c simulation
    -->c synthesis
    -->c/rtl co-simulation
    -->export ip

    ->VIVADO DESIGN SUITE
    -->create block design
    -->generate output file
    -->generate hdl wrapper
    -->generate bitstream
    -->export hardware
    -->launch sdk

    ->XILINX SDK
    -->create bsp
    -->create application

    Now I have some questions:

    - If I want to use the PCAP interface to partially reconfigure the PL run-time how have I to modify the work-flow?

    - Have I to add some specific block in the block design to be able to use the PCAP?

    Thanks in advance

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