PL pin assignment?

Hello all,

I have recently purchased a Zedboard and now trying to make a small design with PS-PL and some custom AXI peripherals with custom VHDL code. What I havent figured out yet is how I assign some output signals to pins on the PL side. I havent found any tutorial on this and I do not know where I can find the process.

Thanks

0 Former Member over 10 years ago

Take a look at Chapter 3 in the ZedBoard Zynq Concepts, Tools and Techniques tutorial for an example of creating a constraints (.xdc) file specifying PL signal pins. You can download the tutorial here:

http://zedboard.org/support/design/1521/11

-Gary
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel
0 zedhed over 10 years ago

Hi opolychr,

In your logic design you may have some top level signals that you wish to connect externally. Those nets must be constrained to physical pin locations through the use of an XDC file which specifies the NET name connection within the logic design as well as the physical pin location that it will be connected to.

There is an example of how to use a constraints file in a design. There is some information on how to include a constraints file in a design within the 2014.2 "Zynq Concepts, Tools, and Techniques on ZedBoard" tutorial on the ZedBoard Reference Design/Tutorials page:

http://microzed.org/support/design/1521/11

Regards,

-Kevin
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel
0 zedhed over 10 years ago

You can also use the ZedBoard Master XDC file found on the Documentation page to get you started with assigning pins to your design.

http://microzed.org/support/documentation/1521

Simply use that file to select the pins you want and rename the associated connecting NET names to match the ones that you want tied to physical pin location.

Regards,

-Kevin
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel
0 opolychr over 10 years ago

Perfect answers all of you!! Thanks a lot!
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel
0 opolychr over 10 years ago

Another question I had is:

How come and Vivado is self concious about the pins in the PS side?

I say that because when I create a new project and I declare the specific Zynq chip but without stating the Zedboard, the connection automation connects the DDR and the fixed pins without a xdf file?

Does that have to do with the fact that the PS side pins are fixed and there is no need for them to be declared explicitla in the xdf file?

Thanks again!
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel